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2020 – today
- 2024
[c10]Nicola Scolari, Franz-Xaver Pengg, Konstantinos Manetakis, Camilo A. Salazar, Alexandre Vouilloz, Ernesto Pérez Serna, Anjana Dissanayake, Pascal Persechini, Vladimir Kopta, Erwan Le Roux, Francesco Chicco, Stefano Cillo, Nicola Gerber, Cédric Barbelenet, Fabio Epifano, Paulo Augusto Dal Fabbro, Nicolas Raemy:
23.2 A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s. ISSCC 2024: 402-404- 2023
- [c9]Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers:
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR. CICC 2023: 1-2 - 2022
- [j5]Anjana Dissanayake
, Henry L. Bishop, Steven M. Bowers, Benton H. Calhoun:
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver. IEEE J. Solid State Circuits 57(3): 917-931 (2022) - 2021
- [j4]Rishika Agarwala, Peng Wang, Henry L. Bishop, Anjana Dissanayake, Benton H. Calhoun:
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. IEEE J. Solid State Circuits 56(4): 1058-1070 (2021) - [c8]Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun:
Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design. ISCAS 2021: 1-4 - [c7]Henry L. Bishop, Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun:
21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms Latency. ISSCC 2021: 310-312 - 2020
- [c6]Anjana Dissanayake, Jesse Moody, Henry L. Bishop, Daniel S. Truesdell, Henry Muhlbauer, Ruochen Lu, Anming Gao, Songbin Gong, Benton H. Calhoun, Steven M. Bowers:
A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver. CICC 2020: 1-4 - [c5]Anjana Dissanayake, Henry L. Bishop, Jesse Moody, Henry Muhlbauer, Benton H. Calhoun, Steven M. Bowers:
A Multichannel, MEMS-Less -99dBm 260nW Bit-Level Duty Cycled Wakeup Receiver. VLSI Circuits 2020: 1-2 - [c4]Peng Wang, Rishika Agarwala, Henry L. Bishop, Anjana Dissanayake, Benton H. Calhoun:
A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j3]Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, Daniel S. Truesdell, Sumanth Kamineni, Benton H. Calhoun:
A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time. IEEE J. Solid State Circuits 54(7): 1952-1959 (2019) - [c3]Jesse Moody, Anjana Dissanayake, Henry L. Bishop, Ruochen Lu, Ningxi Liu, Divya Duvvuri, Anming Gao, Daniel S. Truesdell, N. Scott Barker, Songbin Gong, Benton H. Calhoun, Steven M. Bowers:
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver. VLSI Circuits 2019: 86- - 2018
- [j2]Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee:
A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1579-1583 (2018) - [c2]Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee:
A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver. ASP-DAC 2018: 319-320 - [c1]Ningxi Liu, Rishika Agarwala, Anjana Dissanayake, Daniel S. Truesdell, Sumanth Kamineni, Xing Chen, David D. Wentzloff, Benton H. Calhoun:
A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time. ESSCIRC 2018: 150-153 - 2017
- [j1]Jusung Kim, Dzuhri Radityo Utomo, Anjana Dissanayake, Seok-Kyun Han, Sang-Gug Lee:
The Evolution of Channelization Receiver Architecture: Principles and Design Challenges. IEEE Access 5: 25385-25395 (2017)
Coauthor Index
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