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2020 – today
- 2024
[j13]Ashwin Sanjay Lele
, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. IEEE J. Solid State Circuits 59(1): 52-64 (2024)- [j12]Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. IEEE J. Solid State Circuits 59(1): 116-127 (2024) - [j11]De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. IEEE J. Solid State Circuits 59(1): 219-230 (2024) - [j10]Akash Levy, Luke R. Upton, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina:
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage. IEEE J. Solid State Circuits 59(7): 2081-2092 (2024) - [j9]Xiaoyu Sun, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong:
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. ACM Trans. Design Autom. Electr. Syst. 29(6): 1-27 (2024) - [c27]Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. ISSCC 2024: 482-484 - [c26]Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices. ISSCC 2024: 568-570 - [c25]Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. ISSCC 2024: 580-582 - [c24]Kartik Prabhu, Robert M. Radway, Y. Jeffrey, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina:
MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating. VLSI Technology and Circuits 2024: 1-2 - [c23]De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. VLSI Technology and Circuits 2024: 1-2 - [i1]Yiwei Zhao, Ziyun Li, Win-San Khwa, Xiaoyu Sun, Sai Qian Zhang, Syed Shakib Sarwar, Kleber Hugo Stangherlin, Yi-Lun Lu, Jorge Tomás Gómez, Jae-Sun Seo, Phillip B. Gibbons, Barbara De Salvo, Chiao Liu:
Neural Architecture Search of Hybrid Models for NPU-CIM Heterogeneous AR/VR Devices. CoRR abs/2410.08326 (2024) - 2023
- [j8]Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. IEEE J. Solid State Circuits 58(1): 303-315 (2023) - [c22]Luke R. Upton, Akash Levy, Michael D. Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann:
EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry. ESSCIRC 2023: 469-472 - [c21]Zexi Ji, Hanrui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P. Chandrakasan:
A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices. ISLPED 2023: 1-6 - [c20]Wei-Hsing Huang, Tai-Hao Wen, Je-Min Hung, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Hung-Hsi Hsu, Yu-Hsiang Chin, Yu-Chiao Chen, Chuna-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. ISSCC 2023: 258-259 - [c19]Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. ISSCC 2023: 426-427 - [c18]Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. ISSCC 2023: 496-497 - [c17]Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. VLSI Technology and Circuits 2023: 1-2 - [c16]Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j7]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE J. Solid State Circuits 57(1): 68-79 (2022) - [j6]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE J. Solid State Circuits 57(3): 845-857 (2022) - [j5]Kartik Prabhu, Albert Gural, Zainab F. Khan, Robert M. Radway, Massimo Giordano, Kalhan Koul, Rohan Doshi, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina:
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. IEEE J. Solid State Circuits 57(4): 1013-1026 (2022) - [j4]Xin Zheng, Ryan Zarcone, Akash Levy, Win-San Khwa, Priyanka Raina, Bruno A. Olshausen, H.-S. Philip Wong:
High-density analog image storage in an analog-valued non-volatile memory array. Neuromorph. Comput. Eng. 2(4): 44018 (2022) - [c15]Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. ISSCC 2022: 1-3 - [c14]Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. ISSCC 2022: 1-3 - [c13]Win-San Khwa, Yen-Cheng Chiu, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang:
A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices. ISSCC 2022: 1-3 - [c12]Samuel D. Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. ISSCC 2022: 1-3 - [c11]Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. ISSCC 2022: 178-180 - 2021
- [j3]Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. IEEE J. Solid State Circuits 56(1): 188-198 (2021) - [c10]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. CICC 2021: 1-2 - [c9]Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. ISSCC 2021: 245-247 - [c8]Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury:
29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. ISSCC 2021: 404-406 - [c7]Massimo Giordano, Kartik Prabhu, Kalhan Koul, Robert M. Radway, Albert Gural, Rohan Doshi, Zainab F. Khan, John W. Kustin, Timothy Liu, Gregorio B. Lopes, Victor Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Guénolé Lallement, Boris Murmann, Subhasish Mitra, Priyanka Raina:
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. VLSI Circuits 2021: 1-2 - 2020
- [c6]Qing Dong, Mahmut E. Sinangil, Burak Erbagci, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang:
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. ISSCC 2020: 242-244
2010 – 2019
- 2019
- [j2]Xin Si, Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xiaoyu Sun, Rui Liu, Shimeng Yu, Hiroyuki Yamauchi, Qiang Li, Meng-Fan Chang:
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4172-4185 (2019) - [c5]Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin:
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. VLSI Circuits 2019: 120- - 2018
- [c4]Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu:
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. DAC 2018: 21:1-21:6 - [c3]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - 2017
- [j1]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew J. BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications. IEEE J. Solid State Circuits 52(1): 218-228 (2017) - [c2]Wei-Hao Chen, Win-San Khwa, Jun-Yi Li, Wei-Yu Lin, Huan-Ting Lin, Yongpan Liu, Yu Wang, Huaqiang Wu, Huazhong Yang, Meng-Fan Chang:
Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing. ISQED 2017: 23-28 - 2016
- [c1]Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew BrightSky, SangBum Kim, Hsiang-Lam Lung, Chung Lam:
7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications. ISSCC 2016: 134-135
Coauthor Index
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