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ORCIDSai Rahul Chalamalasetti
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- affiliation: Hewlett Packard Enterprise Labs, Palo Alto, CA, USA
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2020 – today
- 2024
[j7]Pedro Bruel
, Sai Rahul Chalamalasetti, Aditya Dhakal, Eitan Frachtenberg, Ninad Hogade, Rolando Pablo Hong Enriquez, Alok Mishra, Dejan S. Milojicic, Pavana Prakash, Gourav Rattihalli:
Predicting Heterogeneity and Serverless Principles of Converged High-Performance Computing, Artificial Intelligence, and Workflows. Computer 57(1): 136-144 (2024)- [c28]Philipp Raith, Gourav Rattihalli, Aditya Dhakal, Sai Rahul Chalamalasetti, Dejan S. Milojicic, Eitan Frachtenberg, Stefan Nastic, Schahram Dustdar:
Opportunistic Energy-Aware Scheduling for Container Orchestration Platforms Using Graph Neural Networks. CCGrid 2024: 299-306 - 2023
- [c27]Tobias Pfandzelter, Aditya Dhakal, Eitan Frachtenberg, Sai Rahul Chalamalasetti, Darel Emmot, Ninad Hogade, Rolando Pablo Hong Enriquez, Gourav Rattihalli, David Bermbach, Dejan S. Milojicic:
Kernel-as-a-Service: A Serverless Programming Model for Heterogeneous Hardware Accelerators. Middleware 2023: 192-206 - 2021
- [c26]Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-Mei W. Hwu, Dejan S. Milojicic:
Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. ASP-DAC 2021: 372-377 - [c25]Plínio Silveira, César Augusto Fonticielha De Rose, Avelino Francisco Zorzo, Miguel Gomes Xavier, Dejan S. Milojicic, Sai Rahul Chalamalasetti, Sergey Serebryakov:
Resource Sharing and Security Implications on Machine Learning Inference Accelerators. COMPSAC 2021: 59-67 - [c24]Sitao Huang, Kun Wu, Sai Rahul Chalamalasetti, Izzat El Hajj, Cong Xu, Paolo Faraboschi, Deming Chen:
A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper). PEHC@SC 2021: 20-26 - 2020
- [j6]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei Hwu, Kaushik Roy:
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM. IEEE Trans. Computers 69(8): 1128-1142 (2020)
2010 – 2019
- 2019
- [c23]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic:
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. ASPLOS 2019: 715-731 - [c22]Martin Foltin, Glaucimar Aguiar, Rodrigo Antunes, Plínio Silveira, Gustavo Knuppe, Joao Ambrosi, Soumitra Chatterjee, Jitendra Onkar Kolhe, Sunil Lakshiminarashimha, Dejan S. Milojicic, John Paul Strachan, Craig Warner, Amit Sharma, Eddie Lee, Sai Rahul Chalamalasetti, Chris Brueggen, Charles Williams, Nathaniel Jansen, Felipe Saenz, Luis Federico Li:
FPGA Demonstrator of a Programmable Ultra-Efficient Memristor-Based Machine Learning Inference Accelerator. ICRC 2019: 44-53 - [c21]Sitao Huang, Li-Wen Chang, Izzat El Hajj, Simon Garcia De Gonzalo, Juan Gómez-Luna, Sai Rahul Chalamalasetti, Mohamed El-Hadedy, Dejan S. Milojicic, Onur Mutlu, Deming Chen, Wen-Mei W. Hwu:
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures. ICPE 2019: 79-90 - [i3]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-Mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic:
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. CoRR abs/1901.10351 (2019) - [i2]Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei W. Hwu, Kaushik Roy:
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM. CoRR abs/1912.11516 (2019) - 2018
- [c20]Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen-Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan S. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plínio Silveira, John Paul Strachan:
Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. ICRC 2018: 1-13 - [c19]Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, Matthew P. Hardy, John Paul Strachan:
Regular Expression Matching with Memristor TCAMs. ICRC 2018: 1-11 - [c18]Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, John Paul Strachan, Matthew P. Hardy:
Regular Expression Matching with Memristor TCAMs for Network Security. NANOARCH 2018: 65-71 - 2017
- [c17]Pedro Bruel, Sai Rahul Chalamalasetti, Chris I. Dalton, Izzat El Hajj, Alfredo Goldman, Catherine Graves, Wen-Mei W. Hwu, Phil Laplante, Dejan S. Milojicic, Geoffrey Ndu, John Paul Strachan:
Generalize or Die: Operating Systems Support for Memristor-Based Accelerators. ICRC 2017: 1-8 - [c16]Pedro Bruel, Alfredo Goldman, Sai Rahul Chalamalasetti, Dejan S. Milojicic:
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp. ReConFig 2017: 1-6 - 2015
- [c15]Nasibeh Nasiri, Oren Segal, Martin Margala, Wim Vanderbauwhede, Sai Rahul Chalamalasetti:
High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL (Abstract Only). FPGA 2015: 274 - 2014
- [c14]Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright:
High level programming framework for FPGAs in the data center. FPL 2014: 1-4 - [i1]Oren Segal, Martin Margala, Sai Rahul Chalamalasetti, Mitch Wright:
High Level Programming for Heterogeneous Architectures. CoRR abs/1408.4964 (2014) - 2013
- [j5]Wim Vanderbauwhede, Anton Frolov, Sai Rahul Chalamalasetti, Martin Margala:
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification. SIGARCH Comput. Archit. News 41(5): 53-58 (2013) - [j4]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1346-1350 (2013) - [j3]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1915-1927 (2013) - [c13]Wim Vanderbauwhede, Anton Frolov, Leif Azzopardi, Sai Rahul Chalamalasetti, Martin Margala:
High throughput filtering using FPGA-acceleration. CIKM 2013: 1245-1248 - [c12]Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala:
An FPGA memcached appliance. FPGA 2013: 245-254 - 2012
- [j2]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Martin Margala:
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application. Int. J. Reconfigurable Comput. 2012: 507173:1-507173:16 (2012) - [c11]Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede, Mitch Wright, Parthasarathy Ranganathan:
Evaluating FPGA-acceleration for real-time unstructured search. ISPASS 2012: 200-209 - 2011
- [c10]Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala:
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. HPCS 2011: 461-467 - 2010
- [j1]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede:
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. IEEE Embed. Syst. Lett. 2(4): 123-126 (2010) - [c9]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. AHS 2010: 59-65 - [c8]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
A C++-embedded Domain-Specific Language for programming the MORA soft processor array. ASAP 2010: 141-148 - [c7]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
Design of self correcting radiation hardened digital circuits using decoupled ground bus. ACM Great Lakes Symposium on VLSI 2010: 405-408
2000 – 2009
- 2009
- [c6]Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede:
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. AHS 2009: 389-396 - [c5]Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit:
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. ERSA 2009: 195-201 - [c4]Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala:
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. FPL 2009: 534-538 - [c3]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala:
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. ACM Great Lakes Symposium on VLSI 2009: 433-436 - 2008
- [c2]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. ReConFig 2008: 217-222 - [c1]Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. SoCC 2008: 375-378
Coauthor Index
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last updated on 2024-10-23 20:29 CEST by the dblp team
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