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2020 – today
- 2025
[j56]Chung-Lun Tu, Chen-Yuan Tseng, Wei-Che Lee, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou:
Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model. IEEE Open J. Circuits Syst. 6: 14-25 (2025)- 2024
- [c100]Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang:
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. DATE 2024: 1-6 - [c99]Chia-Jung Lee, Chung-Lun Tu, Shyh-Jye Jou:
Online Self-Adaptive Estimation and Compensation Design for DC Voltage Offset, Frequency-Independent, and Frequency-Dependent IQ Mismatch in Sub-THz Digital Baseband Transceiver. ISCAS 2024: 1-5 - [c98]Feng-Ju Liao, Chung-Lun Tu, Shyh-Jye Jou:
Channel Estimation and Equalization Design with SNR Decision Based Universal Threshold for Sub-THz Single Carrier Baseband Receiver. ISCAS 2024: 1-5 - [c97]Tsung-Han Wu, Ching Liang Yeh, Yi-Shan Huang, Shyh-Jye Jou:
A 128 Gb/s LDPC Decoder Using Partial Syndrome-based Dynamic Decoding Scheme for Terahertz Wireless Multi-Media Networks. ISCAS 2024: 1-5 - [c96]Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai:
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. MWSCAS 2024: 1085-1090 - 2023
- [j55]Chih-Wei Jen
, Hung-Chih Liu, Zheng-Chun Huang, Nai-Cheng Xue, Shyh-Jye Jou:
A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(2): 461-475 (2023) - [j54]Henry Lopez Davila, Tsung-Han Wu, Shyh-Jye Jou, Sau-Gee Chen, Pei-Yun Tsai:
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 29-42 (2023) - [c95]Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC 2023: 352-357 - [c94]Chung-Lun Tu, Chin-Ming Chang, Shyh-Jye Jou:
Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter. ISCAS 2023: 1-5 - 2022
- [j53]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(2): 547-556 (2022) - [j52]Hung-Chih Liu, Zheng-Chun Huang, Ngoc-Giang Doan, Chih-Wei Jen, Shyh-Jye Jou:
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 919-932 (2022) - [j51]Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou:
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1184-1192 (2022) - [c93]Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou:
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. DATE 2022: 208-213 - [c92]Kang-Lun Chiu, Hsun-Wei Chan, Hsuan-Ping Chiu, Chun-Yi Liu, Chih-Wei Jen, Shyh-Jye Jou:
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique. ISCAS 2022: 742-746 - [c91]Shen-Zhe Lu, Nai-Cheng Xue, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou:
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter. ISCAS 2022: 1541-1545 - [c90]Chung-Lun Tu, Tse-Yuan Lin, Kang-Lun Chiu, Shyh-Jye Jou, Pei-Yun Tsai:
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System. ISCAS 2022: 2496-2500 - [c89]Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD 2022: 1-4 - [c88]Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT 2022: 1-4 - [i2]Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou:
Hardware-Robust In-RRAM-Computing for Object Detection. CoRR abs/2205.03996 (2022) - [i1]Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou:
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization. CoRR abs/2205.04665 (2022) - 2021
- [j50]Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou:
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 904-915 (2021) - [c87]Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou:
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. ISCAS 2021: 1-5 - [c86]Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC 2021: 262-263 - [c85]Yu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang, Jia-Yin Chen, Shyh-Jye Jou:
A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. VLSI-DAT 2021: 1-2 - 2020
- [j49]Kang-Lun Chiu, Pai-Hsiang Shen, Bing-Ru Lin, Wei-Han Hsiao, Shyh-Jye Jou, Chia-Chi Huang:
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3211-3223 (2020) - [j48]Henry Lopez Davila, Hsun-Wei Chan, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou:
A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 926-939 (2020) - [c84]Hung-Chih Liu, Hsun-Wei Chan, Henry Lopez Davila, Kang-Lun Chiu, Chih-Wei Jen, Ngoc-Giang Doan, Zheng-Chun Huang, Hsin-Ting Chang, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou:
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC. A-SSCC 2020: 1-2 - [c83]Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD 2020: 127:1-127:8 - [c82]Ngoc-Giang Doan, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou:
Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c81]Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou:
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. ASICON 2019: 1-4 - [c80]C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh:
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line. A-SSCC 2019: 227-230 - [c79]Kang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng-Yuan Huang, Chun-Yi Liu, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou:
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications. A-SSCC 2019: 275-278 - [c78]Chee-Kit Ng, Kang-Lun Chiu, Yu-Chun Lin, Shyh-Jye Jou:
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems. ISCAS 2019: 1-5 - [c77]Chee-Kit Ng, Yu-Chun Lin, Shyh-Jye Jou:
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems. VLSI-DAT 2019: 1-4 - 2018
- [c76]Chih-Wei Jen, Hung-Wei Yang, Hsun-Wei Chan, Hung-Chih Liu, Henry Lopez Davila, Chun-Yi Liu, Shyh-Jye Jou:
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band. ISCAS 2018: 1-4 - [c75]Chee-Kit Ng, Yu-Chun Lin, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou:
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems. ISCAS 2018: 1-4 - 2017
- [j47]Chun-Yi Liu, Edmund Wen Jen Leong, Chang-Ting Wu, Meng-Siou Sie, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou:
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 558-568 (2017) - [j46]Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou:
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 608-618 (2017) - [c74]Hsun-Wei Chan, Chang-Ting Wu, Chih-Wei Jen, Chun-Yi Liu, Wei-Che Lee, Shyh-Jye Jou:
A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver. ASICON 2017: 643-646 - [c73]Chun-Yi Liu, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou:
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band. ISCAS 2017: 1-4 - 2016
- [j45]Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou:
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series. Circuits Syst. Signal Process. 35(8): 2972-2991 (2016) - [j44]Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou:
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. IEICE Trans. Electron. 99-C(4): 481-490 (2016) - [j43]Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou:
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. 24(8): 1380-1392 (2016) - [j42]Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Henry Lopez Davila, Chih-Wei Jen, Wei-Chang Liu, Shyh-Jye Jou:
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2347-2356 (2016) - [j41]Chih-Feng Wu, Wei-Chang Liu, Chia-Chun Tsui, Chun-Yi Liu, Meng-Siou Sie, Shyh-Jye Jou:
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3323-3333 (2016) - [c72]Hung-Wei Yang, Yongyu He, Chih-Wei Jen, Chun-Yi Liu, Shyh-Jye Jou, Xuefeng Yin, Meng Ma, Bingli Jiao:
Interference measurement and analysis of full-duplex wireless system in 60 GHz band. APCCAS 2016: 273-276 - [c71]Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou:
Error-resilient sequential cells with successive time borrowing for stochastic computing. ICASSP 2016: 6545-6549 - [c70]Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang:
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS 2016: 1014-1017 - [c69]Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Shyh-Jye Jou:
A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver. ISCAS 2016: 2655-2658 - 2015
- [j40]Chia-Wen Chang, Yuan-Hua Chu, Shyh-Jye Jou:
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. IEICE Trans. Electron. 98-C(8): 882-891 (2015) - [j39]Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou:
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 545-553 (2015) - [j38]Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 743-751 (2015) - [j37]Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou:
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2052-2061 (2015) - [j36]Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen:
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 766-770 (2015) - [j35]Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 958-962 (2015) - [c68]Wen-Quan He, Yu-Chun Lin, Jui-Yi Hung, Shyh-Jye Jou:
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead. ASICON 2015: 1-4 - [c67]Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu, Shyh-Jye Jou:
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. A-SSCC 2015: 1-4 - [c66]Pranav Arya, Liang-Yu Huang, Wei-Chang Liu, Hsin-Ting Chang, Chih-Wei Jen, Chih-Feng Wu, Shyh-Jye Jou:
Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system. ICCE-TW 2015: 204-205 - [c65]Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. ISCAS 2015: 2549-2552 - [c64]Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, Shyh-Jye Jou, Sau-Gee Chen:
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems. SoCC 2015: 44-48 - [c63]Liang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou:
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems. VLSI-DAT 2015: 1-4 - 2014
- [j34]Chih-Wei Jen, Shyh-Jye Jou:
Blind ICA detection based on second-order cone programming for MC-CDMA systems. EURASIP J. Adv. Signal Process. 2014: 151 (2014) - [j33]Cheng-Wen Wei, Cheng-Chun Tsai, FanJiang Yi, Tian-Sheuan Chang, Shyh-Jye Jou:
Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application. IET Circuits Devices Syst. 8(6): 516-525 (2014) - [j32]Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang:
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing. IEEE ACM Trans. Audio Speech Lang. Process. 22(8): 1248-1259 (2014) - [j31]Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang:
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing". IEEE ACM Trans. Audio Speech Lang. Process. 22(12): 2256 (2014) - [j30]Yu-Jui Chen, Cheng-Wen Wei, Yi FanChiang, Yi-Le Meng, Yi-Cheng Huang, Shyh-Jye Jou:
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(2): 463-475 (2014) - [j29]Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang:
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2578-2585 (2014) - [j28]Sau-Gee Chen, Shen-Jui Huang, Mario Garrido, Shyh-Jye Jou:
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2869-2877 (2014) - [j27]Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3416-3425 (2014) - [c62]Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou:
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. ICASSP 2014: 2639-2643 - [c61]Wei-Chang Liu, Fu-Chun Yeh, Chia-Yi Wu, Ting-Chen Wei, Ya-Shiue Huang, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen:
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band. ISCAS 2014: 1006-1009 - [c60]Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou:
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS 2014: 2543-2546 - [c59]Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. SoCC 2014: 160-164 - [c58]Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC 2014: 455-462 - 2013
- [j26]Li-Rong Wang, Kai-Yu Lo, Shyh-Jye Jou:
A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design. IEICE Trans. Electron. 96-C(10): 1351-1355 (2013) - [j25]Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ching-Da Chan, Shyh-Jye Jou:
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2730-2739 (2013) - [j24]Hsiao-Yun Chen, Wei-Kai Chang, Shyh-Jye Jou:
A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10): 2763-2773 (2013) - [j23]Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou:
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 43-54 (2013) - [c57]Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou:
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. CICC 2013: 1-4 - [c56]Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ya-Shiue Huang, Tai-Yang Liu, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen:
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c. ISCAS 2013: 793-796 - [c55]Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih:
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS 2013: 1468-1471 - [c54]Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang:
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED 2013: 51-56 - [c53]Yi-Cheng Huang, Fan-Chiang Yi, Shyh-Jye Jou:
A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids. SiPS 2013: 48-53 - [c52]Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou:
Spatial-cue-based multi-band binaural noise reduction for hearing aids. SiPS 2013: 278-283 - [c51]Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu:
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC 2013: 110-115 - [c50]Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou:
Power and area reduction in multi-stage addition using operand segmentation. VLSI-DAT 2013: 1-4 - 2012
- [j22]Yu-Chun Lin, Shyh-Jye Jou, Muh-Tian Shiue:
High throughput concurrent lookahead adaptive decision feedback equaliser. IET Circuits Devices Syst. 6(1): 52-62 (2012) - [j21]Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang:
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits 47(6): 1469-1482 (2012) - [j20]Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47(9): 2246-2257 (2012) - [j19]Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 863-867 (2012) - [j18]Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou:
Sub µW Noise Reduction for CIC Hearing Aids. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 937-947 (2012) - [c49]Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS 2012: 116-119 - [c48]Jhih-Cing Sun, Jou-Ling Chen, Yi-Hung Shen, Shiu-Chain You, Shyh-Jye Jou, Tzu-Hsien Sang:
A 80-uW 2-Mb/s transceiver for human body channel binaural communication. BioCAS 2012: 96-99 - [c47]Jou-Ling Chen, Jhih-Cing Sun, Yi-Hung Shen, Tzu-Hsien Sang, Tian-Sheuan Chang, Shyh-Jye Jou:
A low-power body-channel communication system for binaural hearing aids. BioCAS 2012: 100-103 - [c46]Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS 2012: 1831-1834 - [c45]Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS 2012: 2485-2488 - [c44]Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang:
Testing strategies for a 9T sub-threshold SRAM. ITC 2012: 1-10 - [c43]Michel Brillouët, Shyh-Jye Jou, C. Patrick Yue:
Welcome from the general chairs. VLSI-DAT 2012: 1 - [c42]Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih:
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - [c41]Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang:
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - 2011
- [j17]Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee:
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. IEICE Trans. Electron. 94-C(6): 1112-1119 (2011) - [c40]Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu:
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. ASICON 2011: 606-609 - [c39]Ming-Chiuan Su, Shyh-Jye Jou:
Digitally-controlled cell-based oscillator with multi-phase differential outputs. ASICON 2011: 610-613 - [c38]Fan-Chiang Yi, Ching-Wen Huang, Tai-Shih Chi, Shyh-Jye Jou:
Low power InfomaxICA with compensation strategy for binaural hearing-aid. ISCAS 2011: 2083-2086 - [c37]Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang:
8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED 2011: 169-174 - [c36]Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu:
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC 2011: 197-200 - 2010
- [j16]Hsiao-Yun Chen, Meng-Lin Ku, Shyh-Jye Jou, Chia-Chi Huang:
A Robust Channel Estimator for High-Mobility STBC-OFDM Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 925-936 (2010) - [j15]Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3039-3047 (2010) - [c35]Cheng-Wen Wei, Cheng-Chun Tsai, Tian-Sheuan Chang, Shyh-Jye Jou:
Perceptual multiband spectral subtraction for noise reduction in hearing aids. APCCAS 2010: 692-695
2000 – 2009
- 2009
- [j14]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 734-738 (2009) - [j13]Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Shyh-Jye Jou:
Low complexity synchronization design of an OFDM receiver for DVB-T/H. IEEE Trans. Consumer Electron. 55(2): 408-413 (2009) - [c34]Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC 2009: 191-194 - [c33]Yu-Chun Lin, Muh-Tian Shiue, Shyh-Jye Jou:
10Gbps Decision Feedback Equalizer with Dynamic Lookahead Decision Loop. ISCAS 2009: 1839-1842 - [c32]Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Asymmetrical Write-assist for single-ended SRAM operation. SoCC 2009: 101-104 - 2008
- [j12]Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43(3): 684-694 (2008) - [j11]Nicky Lu, Shyh-Jye Jou:
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07). IEEE J. Solid State Circuits 43(11): 2352-2353 (2008) - [j10]Wei-Ting Chen, Wei-Chang Liu, Shyh-Jye Jou:
A jointed mode detection and symbol detection scheme for DVB-T. IEEE Trans. Consumer Electron. 54(2): 336-341 (2008) - [c31]Ting-Chen Wei, Wei-Chang Liu, Chi-Yao Tseng, Syu-Siang Long, Shyh-Jye Jou, Muh-Tian Shiue:
A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization. CICC 2008: 351-354 - [c30]Jyun-Nan Lin, Hsiao-Yun Chen, Ting-Chen Wei, Shyh-Jye Jou:
Symbol and carrier frequency offset synchronization for IEEE802.16e. ISCAS 2008: 3082-3085 - [c29]Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee:
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS 2008: 3426-3429 - 2007
- [j9]Shyh-Jye Jou, Chih-Hsien Lin, Yen-Hung Chen, Zheng-Hong Li:
Design and analysis of digital data recovery circuits using oversampling. IET Circuits Devices Syst. 1(1): 95-101 (2007) - [c28]Chi-Shiung Lin, Yu-Chun Lin, Shyh-Jye Jou, Mun-Tian Shiou:
Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System. CICC 2007: 289-292 - [c27]Hsiao-Yun Chen, Shyh-Jye Jou:
Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications. ICASSP (3) 2007: 1473-1476 - [c26]Wei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou:
Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H. ISCAS 2007: 2092-2095 - [c25]Jiun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, Shyh-Jye Jou:
Mixed-VTH (MVT) CMOS circuit design for low power cell libraries. SoCC 2007: 181-184 - 2006
- [j8]Chih-Hsien Lin, Chih-Ning Chen, You-Jiun Wang, Ju-Yuan Hsiao, Shyh-Jye Jou:
Parallel scrambler for high-speed applications. IEEE Trans. Circuits Syst. II Express Briefs 53-II(7): 558-562 (2006) - [j7]Hsiao-Yun Chen, Chih-Hsien Lin, Shyh-Jye Jou:
DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling. IEEE Trans. Circuits Syst. II Express Briefs 53-II(9): 827-831 (2006) - [c24]Ting-Zhen Wei, Shyh-Jye Jou, Muh-Tian Shiue:
Memory reduction ICFO estimation architecture for DVB-T. ISCAS 2006 - 2005
- [j6]Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou:
Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link. IEICE Trans. Electron. 88-C(10): 2009-2019 (2005) - [c23]Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang:
A 12.5 Gbps CMOS input sampler for serial link receiver front end. ISCAS (2) 2005: 1055-1058 - 2004
- [c22]Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu:
A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ISCAS (5) 2004: 293-296 - [c21]Chih-Hsien Lin, Chang-Hsiao Tsai, Chih-Ning Chen, Shyh-Jye Jou:
4/2 PAM serial link transmitter with tunable pre-emphasis. ISCAS (1) 2004: 952-958 - 2003
- [j5]Ya-Lan Tsao, Wei-Hao Chen, Ming Hsuan Tan, Maw-Ching Lin, Shyh-Jye Jou:
Low-Power Embedded DSP Core for Communication Systems. EURASIP J. Adv. Signal Process. 2003(13): 1355-1370 (2003) - [c20]Ja-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou:
Low-power digital CDMA receiver. ASP-DAC 2003: 581-582 - [c19]Chih-Hsien Lin, Chung-Hong Wang, Shyh-Jye Jou:
5Gbps serial link transmitter with pre-emphasis. ASP-DAC 2003: 795-800 - [c18]Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou:
Parameterized and low power DSP core for embedded systems. ISCAS (5) 2003: 265-268 - 2002
- [c17]Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao:
An embedded DSP core for wireless communication. ISCAS (4) 2002: 524-527 - [c16]Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou:
Sub-word and reduced-width Booth multipliers for DSP applications. ISCAS (3) 2002: 575-578 - 2001
- [j4]Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Tin-Hao Lin:
Low switching noise and load-adaptive output buffer design techniques. IEEE J. Solid State Circuits 36(8): 1239-1249 (2001) - [j3]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Intrinsic response for analog module testing using an analog testability bus. ACM Trans. Design Autom. Electr. Syst. 6(2): 226-243 (2001) - [c15]Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu:
A serial link transceiver for USB2 high-speed mode. ISCAS (4) 2001: 72-75 - [c14]Maw-Ching Lin, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou:
Low-power multiplierless FIR filter synthesizer based on CSD code. ISCAS (4) 2001: 666-669 - 2000
- [c13]Shyh-Jye Jou, Hui-Hsuan Wang:
Fixed-Width Multiplier for DSP Application. ICCD 2000: 318-322
1990 – 1999
- 1999
- [j2]Chauchin Su, Shyh-Jye Jou:
Decentralized BIST Methodology for System Level Interconnects. J. Electron. Test. 15(3): 255-265 (1999) - 1998
- [c12]Shyh-Jye Jou, Wei-Chung Cheng, Yu-Tao Lin:
Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]. CICC 1998: 545-548 - [c11]Shyh-Jye Jou, Ya-Lan Tsao, I-Ying Yang:
An all digital phase-locked loop with modified binary search of frequency acquisition. ICECS 1998: 195-198 - 1997
- [j1]Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su:
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. IEEE J. Solid State Circuits 32(1): 114-118 (1997) - [c10]Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou:
Structural approach for performance driven ECC circuit synthesis. ASP-DAC 1997: 89-94 - [c9]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou:
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. ITC 1997: 499-508 - 1996
- [c8]Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting:
Syndrome Simulation And Syndrome Test For Unscanned Interconnects. Asian Test Symposium 1996: 62-67 - [c7]Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting:
Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. ED&TC 1996: 120-125 - [c6]Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting:
Metrology for analog module testing using analog testability bus. ICCAD 1996: 594-599 - 1995
- [c5]Chauchin Su, Shenshung Chiang, Shyh-Jye Jou:
Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ICCAD 1995: 631-636 - [c4]Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su:
A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. ISCAS 1995: 574-577 - [c3]Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su:
Circuits Design Optimization Using Symbolic Approach. ISCAS 1995: 1396-1399 - 1994
- [b1]Resve A. Saleh, Shyh-Jye Jou, A. Richard Newton:
Mixed-mode simulation and analog multilevel simulation. The Kluwer international series in engineering and computer science, Kluwer 1994, ISBN 978-0-7923-9473-0, pp. I-XI, 1-302 - [c2]Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang:
Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. ISCAS 1994: 21-24 - [c1]Chauchin Su, Kychin Hwang, Shyh-Jye Jou:
An IDDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment. ITC 1994: 670-676
Coauthor Index
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