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2020 – today
- 2022
[j9]I-Wen Wu
, Tsung-Hsien Tsai, Chi-Jen Lo, Yi-Ju Chou, Chi-Hsiao Yeh, Yun-Hsuan Chan, Jun-Hong Chen, Paul Wei-Che Hsu, Heng-Chih Pan, Heng-Jung Hsu, Chun-Yu Chen, Chin-Chan Lee, Yu-Chiau Shyu, Chih-Lang Lin, Mei-Ling Cheng, Chi-Chun Lai, Huey-Kang Sytwu, Ting-Fen Tsai:
Discovering a trans-omics biomarker signature that predisposes high risk diabetic patients to diabetic kidney disease. npj Digit. Medicine 5 (2022)- [c15]Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. ISSCC 2022: 1-3 - 2021
- [j8]Tsung-Hsien Tsai, Jun-Wei Hsieh, Chuan-Wang Chang, Chin-Rong Lay, Kuo-Chin Fan:
Air-writing recognition using reverse time ordered stroke context. J. Vis. Commun. Image Represent. 78: 103065 (2021) - [j7]Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1881-1891 (2021) - 2020
- [j6]Tsung-Hsien Tsai:
Self-evolutionary sibling models to forecast railway arrivals using reservation data. Eng. Appl. Artif. Intell. 96: 103960 (2020) - [c14]Wei-Chih Chen, Chin-Hua Wen, Chin-Ming Fu, Tsung-Hsien Tsai, Yu-Chi Chen, Wen-Hung Huang, Chien-Chun Tsai, Alvin Leng Sun Loke, C. H. Kenny:
A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS. VLSI Circuits 2020: 1-2 - [c13]Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen:
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c12]Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski:
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. VLSI Circuits 2018: 183-184 - 2017
- [j5]Chin-Liang Wang, Ting-Nan Cho, Tsung-Hsien Tsai, Min-Chau Jan:
A Cooperative Multihop Transmission Scheme for Two-Way Amplify-and-Forward Relay Networks. IEEE Trans. Veh. Technol. 66(9): 8569-8574 (2017) - [c11]Tsung-Hsien Tsai, Jun-Wei Hsieh:
Air-writing recognition using reverse time ordered stroke context. ICIP 2017: 4137-4141 - 2016
- [j4]Yunchan Chi, Tsung-Hsien Tsai, Yi-Hsuan Tu, Wen-Yan Tsai:
Comparison of Several Confidence Intervals for Median Residual Lifetime with Left-truncated and Right-censored Data. Commun. Stat. Simul. Comput. 45(2): 701-716 (2016) - [c10]Tsung-Hsien Tsai, Kuochen Wang, Tzu-Yu Chao:
Dynamic flow aggregation in SDNs for application-aware routing. CSNDSP 2016: 1-5 - [c9]Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2 - 2015
- [c8]Li-Chih Chen, Jun-Wei Hsieh, Hui-Fen Chiang, Tsung-Hsien Tsai:
Real-time vehicle color identification using symmetrical SURFs and chromatic strength. ISCAS 2015: 2804-2807 - [c7]Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski:
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. ISSCC 2015: 1-3 - 2013
- [c6]Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan:
A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. CICC 2013: 1-4 - [c5]Yu-Kumg Chen, Tsung-Hsien Tsai:
A new sky recognition with using location of sky subimage. ICIA 2013: 1103-1108 - [c4]Yu-Kumg Chen, Tsung-Hsien Tsai:
Sky recognitions for driving-view images. ICVES 2013: 119-124 - 2010
- [j3]Nelson Yen-Chung Chang, Tsung-Hsien Tsai, Po-Hsiung Hsu, Yi-Chun Chen, Tian-Sheuan Chang:
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight. IEEE Trans. Circuits Syst. Video Technol. 20(6): 792-805 (2010)
2000 – 2009
- 2009
- [j2]Tsung-Hsien Tsai, Chi-Kang Lee, Chien-Hung Wei:
Neural network based temporal feature models for short-term railway passenger demand forecasting. Expert Syst. Appl. 36(2): 3728-3736 (2009) - [j1]Tsung-Hsien Tsai:
A temporal case retrieval model to predict railway passenger arrivals. Expert Syst. Appl. 36(5): 8876-8882 (2009) - 2008
- [c3]Tsung-Hsien Tsai:
Case Based Models to Predict Final Sales: A Test of Railway Passenger Arrivals. DMIN 2008: 243-248 - [c2]Tsung-Hsien Tsai, Nelson Yen-Chung Chang, Tian-Sheuan Chang:
Data reuse analysis of local stereo matching. ISCAS 2008: 812-815 - 2007
- [c1]Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang:
Real-Time DSP Implementation on Local Stereo Matching. ICME 2007: 2090-2093
Coauthor Index
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