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2020 – today
- 2023
[c13]Lucas Antunes Tambara
, Pascal Masson, Julien Amouroux, Stéphane Monfray, Julien Dura, Frederic Gianesello, Julien Babic, Romain Debroucke, Loic Welter, Siddhartha Dhar, Bernadette Gros, Clement Charbuillet, Franck Julien, Guillaume Bertrand, Arnaud Régnier, Alain Fleury:
Notched gate MOSFET for capacitance reduction in RF SOI technology. DTTIS 2023: 1-4
2010 – 2019
- 2019
- [c12]Fabio Benevenuti, Eduardo Chielle, Jorge L. Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Carlos Alberto Zaffari, João Baptista dos Santos Martins, Otávio Santos Cupertino Durão:
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission. IPDPS Workshops 2019: 140-146 - 2017
- [j3]Jorge L. Tonfat, Lucas A. Tambara, André Santos, Fernanda Lima Kastensmidt:
Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs. Microprocess. Microsystems 51: 209-219 (2017) - [j2]Lucas A. Tambara, Eduardo Chielle, Fernanda Lima Kastensmidt, Georgios Tsiligiannis, Salvatore Danzeca, Markus Brugger, A. Masi:
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment. Microelectron. Reliab. 76-77: 640-643 (2017) - [c11]Ádria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt:
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC. ARC 2017: 189-201 - [c10]André Flores dos Santos, Lucas Antunes Tambara, Fabio Benevenuti, Jorge L. Tonfat, Fernanda Lima Kastensmidt:
Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs. ARC 2017: 202-213 - [c9]Ádria Barros de Oliveira, Lucas Antunes Tambara, Fernanda Lima Kastensmidt:
Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors. LASCAS 2017: 1-4 - [c8]André Flores dos Santos, Lucas Antunes Tambara, Fernanda Lima Kastensmidt:
Evaluating the efficiency of using TMR in the high-level synthesis design flow of SRAM-based FPGA. LASCAS 2017: 1-4 - 2016
- [c7]Jorge L. Tonfat, Lucas A. Tambara, André Flores dos Santos, Fernanda Gusmão de Lima Kastensmidt:
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors. ARC 2016: 132-143 - 2015
- [j1]Cristiano P. Chenet, Lucas A. Tambara, Gabriel de M. Borges, Fernanda Lima Kastensmidt, Marcelo Soares Lubaszewski, Tiago R. Balen:
Exploring design diversity redundancy to improve resilience in mixed-signal systems. Microelectron. Reliab. 55(12): 2833-2844 (2015) - [c6]Lucas A. Tambara, Felipe Almeida, Paolo Rech, Fernanda Lima Kastensmidt, Giovanni Bruni, Christopher Frost:
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects. ARC 2015: 331-338 - [c5]Jimmy Tarrillo, Jorge L. Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Ricardo Reis:
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments. LATS 2015: 1-6 - 2014
- [c4]Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Christopher Frost:
Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs. DFT 2014: 153-158 - [c3]Lucas A. Tambara, Jorge L. Tonfat, Ricardo Reis, Fernanda Lima Kastensmidt, Evaldo Carlos Fonseca Pereira, Rafael Galhardo Vaz, Odair Lelis Goncalez:
Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects. LATW 2014: 1-6 - [c2]Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Alessandro Paccagnella:
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. VLSI-SoC 2014: 1-6 - 2013
- [c1]Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Tiago R. Balen, Marcelo Lubaszewski:
Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC. ISVLSI 2013: 188-193
Coauthor Index
aka: Fernanda Gusmão de Lima Kastensmidt
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