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ORCIDJohn Jose
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- Jose John
- John Anthony Jose (aka: John Anthony C. Jose)
- John Jose Prabhu Joseph
- John-Jose Nunez
- José John Fredy González Veloza
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2020 – today
- 2024
[j22]Syam Sankar
, Ruchika Gupta, John Jose, Sukumar Nandi:
Sec-NoC: A Lightweight Secure Communication System for On-Chip Interconnects. IEEE Embed. Syst. Lett. 16(2): 214-217 (2024)- [j21]Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose:
Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip. J. Circuits Syst. Comput. 33(12): 2450207:1-2450207:33 (2024) - [j20]Syam Sankar, Ruchika Gupta, John Jose, Sukumar Nandi:
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans. ACM Trans. Design Autom. Electr. Syst. 29(2): 34:1-34:25 (2024) - [j19]S. Sivakumar, John Jose, Vijaykrishnan Narayanan:
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers. ACM Trans. Design Autom. Electr. Syst. 29(3): 58:1-58:24 (2024) - [c53]Manju Rajan, Arya Phadke, Syam Sankar, John Jose:
Handling Packet Blocking Attack in NoC Using Traffic Snooping. COINS 2024: 1-6 - [c52]Amit Puri, Kartheek Bellamkonda, Kailash Narreddy, John Jose, Venkatesh Tamarapalli, Vijaykrishnan Narayanan:
DRackSim: Simulating CXL-enabled Large-Scale Disaggregated Memory Systems. SIGSIM-PADS 2024: 3-14 - 2023
- [j18]K. Neethu, K. C. Sharin Shahana, Rekha K. James, John Jose, Sumit K. Mandal:
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training. IEEE Des. Test 40(6): 51-63 (2023) - [j17]Manju Rajan, Mayank Choksey, John Jose:
Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip. J. Syst. Archit. 144: 103006 (2023) - [j16]Rose George Kunthara, V. R. Josna, K. Neethu, Rekha K. James, John Jose:
Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks. SN Comput. Sci. 4(3): 284 (2023) - [j15]Dipika Deb, John Jose:
ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs. ACM Trans. Embed. Comput. Syst. 22(5s): 118:1-118:25 (2023) - [j14]S. Sivakumar, John Jose:
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC. ACM Trans. Design Autom. Electr. Syst. 28(6): 97:1-97:24 (2023) - [c51]Maurizio Palesi, Enrico Russo, Abhijit Das, John Jose:
Wireless enabled Inter-Chiplet Communication in DNN Hardware Accelerators. IPDPS Workshops 2023: 477-483 - [c50]Syam Sankar, Lissiyas Antony, Ruchika Gupta, John Jose, Sukumar Nandi:
Exploring Trustable Paths in Network-on-Chip for Low-Slack Packets. ISOCC 2023: 85-86 - [c49]Amit Puri, Abir Banerjee, John Jose, Tamarapalli Venkatesh:
Understanding the Performance Impact of Queue-Based Resource Allocation in Scalable Disaggregated Memory Systems. MCSoC 2023: 317-324 - [c48]Sachin Bagga, Ruchika Gupta, John Jose:
PortBlocker: Detection and Mitigation of Hardware Trojan through Re-routing and Bypassing. MCSoC 2023: 325-331 - [c47]V. R. Josna, Rose George Kunthara, Rekha K. James, John Jose:
Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip. MCSoC 2023: 426-432 - [c46]Syam Sankar, John Jose, Ruchika Gupta, Sukumar Nandi:
Enhancing Anonymity in NoC Communication to Counter Traffic Profiling by Hardware Trojans. MCSoC 2023: 560-567 - [c45]Amit Puri, Kartheek Bellamkonda, Kailash Narreddy, John Jose, Tamarapalli Venkatesh:
A Practical Approach For Workload-Aware Data Movement in Disaggregated Memory Systems. SBAC-PAD 2023: 78-88 - [c44]Thejaswini P, Sahana A. R., Shankar Singh C., John Jose:
Strengthening NoC Security: Leveraging Hybrid Encryption for Data Packet Protection. TENCON 2023: 738-743 - [i4]Amit Puri, John Jose, Tamarapalli Venkatesh:
Design and Evaluation of a Rack-Scale Disaggregated Memory Architecture For Data Centers. CoRR abs/2303.06420 (2023) - [i3]Amit Puri, John Jose, Tamarapalli Venkatesh, Vijaykrishnan Narayanan:
DRackSim: Simulator for Rack-scale Memory Disaggregation. CoRR abs/2305.09977 (2023) - 2022
- [j13]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Revising NoC in Future Multicore-Based Consumer Electronics for Performance. IEEE Consumer Electron. Mag. 11(3): 79-86 (2022) - [j12]Sudeep Pasricha, John Jose, Sujay Deb:
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures. IEEE Des. Test 39(6): 90-98 (2022) - [j11]Dipika Deb, Rohith M. K., John Jose:
FlitZip: Effective Packet Compression for NoC in MultiProcessor System-on-Chip. IEEE Trans. Parallel Distributed Syst. 33(1): 117-128 (2022) - [c43]Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose:
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. ACM Great Lakes Symposium on VLSI 2022: 211-216 - [c42]Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi:
Securing On-chip Interconnect against Delay Trojan using Dynamic Adaptive Caging. ACM Great Lakes Symposium on VLSI 2022: 411-416 - [c41]Amit Puri, John Jose, Tamarapalli Venkatesh:
Design and Evaluation of a Rack-Scale Disaggregated Memory Architecture For Data Centers. HPCC/DSS/SmartCity/DependSys 2022: 212-217 - [c40]Manju Rajan, Abhijit Das, John Jose:
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC. ISVLSI 2022: 176-181 - [c39]Abhijit Das, John Jose:
Designing Data-Aware Network-on-Chip for Performance. ISVLSI 2022: 428-433 - [c38]Mohammad Humam Khan, Ruchika Gupta, Vedika J. Kulkarni, John Jose, Sukumar Nandi:
Hardware Trojan Mitigation for Securing On-chip Networks from Dead Flit Attacks. VLSI-SoC 2022: 1-6 - [c37]Yogesh Kumar, S. Sivakumar, John Jose:
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. VLSI-SoC 2022: 1-6 - [c36]Akshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose:
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. VLSI-SoC 2022: 1-6 - [i2]Sudeep Pasricha, John Jose, Sujay Deb:
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures. CoRR abs/2208.09070 (2022) - 2021
- [j10]Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose:
Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. Nano Commun. Networks 27: 100334 (2021) - [j9]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty. IEEE Trans. Computers 70(6): 892-905 (2021) - [j8]Dipika Deb, John Jose, Maurizio Palesi:
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. 26(3): 17:1-17:31 (2021) - [j7]Abhijit Das, John Jose, Prabhat Mishra:
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1675-1679 (2021) - [c35]S. Sivakumar, T. M. Abdul Khader, John Jose:
Improving Lifetime of Non-Volatile Memory Caches by Logical Partitioning. ACM Great Lakes Symposium on VLSI 2021: 123-128 - [c34]Mohammad Humam Khan, Ruchika Gupta, John Jose, Sukumar Nandi:
Dead flit attack on NoC by hardware trojan and its impact analysis. NoCArc@MICRO 2021: 10-15 - [c33]Vedika J. Kulkarni, Manju Rajan, Ruchika Gupta, John Jose, Sukumar Nandi:
Packet header attack by hardware trojan in NoC based TCMP and its impact analysis. NOCS 2021: 21-28 - [i1]Abhijit Das, John Jose, Prabhat Mishra:
Data Criticality in Multi-Threaded Applications: An Insight for Many-Core Systems. CoRR abs/2101.00055 (2021) - 2020
- [j6]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose, Valerio Mario Salerno:
Exploiting Data Resilience in Wireless Network-on-chip Architectures. ACM J. Emerg. Technol. Comput. Syst. 16(2): 21:1-21:27 (2020) - [c32]Abhijit Das, Abhishek Kumar, John Jose:
Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers. ICCD 2020: 230-238 - [c31]Joe Augustine, Kanakagiri Raghavendra, John Jose, Madhu Mutyam:
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors. ICCD 2020: 239-246 - [c30]Giuseppe Ascia, Vincenzo Catania, John Jose, Salvatore Monteleone, Maurizio Palesi, Davide Patti:
Improving Inference Latency and Energy of Network-on-Chip based Convolutional Neural Networks through Weights Compression. IPDPS Workshops 2020: 54-63 - [c29]Abhijit Das, Abhishek Kumar, John Jose, Maurizio Palesi:
Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors. ISVLSI 2020: 147-152 - [c28]Manju Rajan, Abhijit Das, John Jose, Prabhat Mishra:
SECTAR: Secure NoC using Trojan Aware Routing. NOCS 2020: 1-8
2010 – 2019
- 2019
- [j5]Dipika Deb, John Jose, Maurizio Palesi:
ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors. IET Comput. Digit. Tech. 13(6): 417-428 (2019) - [j4]Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor:
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. 123: 118-129 (2019) - [c27]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices. IoTSMS 2019: 227-234 - [c26]Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose:
Asymmetric routing in 3D NoC using interleaved edge routers. NoCArc@MICRO 2019: 4:1-4:6 - [c25]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Analyzing networks-on-chip based deep neural networks. NOCS 2019: 23:1-23:2 - [c24]Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, John Jose:
DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip. TENCON 2019: 400-405 - [c23]Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose:
2L-2D Routing for Buffered Mesh Network-on-Chip. VDAT 2019: 308-320 - [c22]Dipika Deb, John Jose, Maurizio Palesi:
Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher. VLSID 2019: 13-18 - 2018
- [j3]Simi Zerine Sleeba, John Jose, Maniyelil Govindankutty Mini:
Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips. IET Comput. Digit. Tech. 12(3): 69-79 (2018) - [c21]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Approximate Wireless Networks-on-Chip. DCIS 2018: 1-6 - [c20]Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose:
ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs. ISED 2018: 204-209 - [c19]Giuseppe Ascia, Vincenzo Catania, Salvatore Monteleone, Maurizio Palesi, Davide Patti, John Jose:
Improving energy consumption of NoC based architectures through approximate communication. MECO 2018: 1-4 - [c18]Abhijit Das, Sarath Babu, John Jose, Sangeetha Jose, Maurizio Palesi:
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks. NOCS 2018: 12:1-12:8 - [c17]K. S. Midhula, Sarath Babu, John Jose, Sangeetha Jose:
Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes. VDAT 2018: 460-472 - [c16]Akshay B. P., Ganesh K. M., Thippeswamy D. R., Vishnu S. Bhat, Anitha Vijayakumar, Ananda Y. R., John Jose:
Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip. VDAT 2018: 495-506 - [c15]Ajay S, Satya Sai Krishna Mohan G, Shashank S Rao, Sujay B Shaunak, Krutthika H. K, Ananda Y. R., John Jose:
Source Hotspot Management in a Mesh Network on Chip. VDAT 2018: 619-630 - [c14]Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini:
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC 2018: 25-30 - [c13]John Jose, Abhijit Das:
An Adaptive Deflection Router with Dual Injection and Ejection Units for Mesh NoCs. VLSID 2018: 374-379 - 2017
- [j2]Elizabeth Isaac, M. Rajasekhara Babu, John Jose:
Impact of deflection history based priority on adaptive deflection router for mesh NoCs. Electron. Gov. an Int. J. 13(4): 391-407 (2017) - [c12]N. S. Aswathy, R. S. Reshma Raj, Abhijit Das, John Jose, V. R. Josna:
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs. VDAT 2017: 337-344 - [c11]R. S. Reshma Raj, Abhijit Das, John Jose:
Implementation and analysis of hotspot mitigation in mesh NoCs by cost-effective deflection routing technique. VLSI-SoC 2017: 1-6 - 2015
- [c10]John Jose, Joe Augustine, Sijin Sebastian:
Dynamic migratory selection strategy for adaptive routing in mesh NoCs. VLSI-SoC 2015: 343-348 - [c9]Reenu James, John Jose, Jobin K. Antony:
Smart Port Allocation for Adaptive NoC Routers. VLSID 2015: 475-480 - 2014
- [j1]John Jose, Madhu Mutyam:
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs. ACM Trans. Design Autom. Electr. Syst. 19(4): 35:1-35:22 (2014) - [c8]Gnaneswara Rao Jonna, John Jose, Rachana Radhakrishnan, Madhu Mutyam:
Minimally buffered single-cycle deflection router. DATE 2014: 1-4 - [c7]Simi Zerine Sleeba, John Jose, Maniyelil Govindankutty Mini:
WeDBless: weighted deflection bufferless router for mesh NoCs. ACM Great Lakes Symposium on VLSI 2014: 77-78 - [c6]Teena Mathew, K. Chandra Sekaran, John Jose:
Study and analysis of various task scheduling algorithms in the cloud computing environment. ICACCI 2014: 658-664 - [c5]John Jose, Bivil M. Jacob, Hashim P. Kamal:
An Energy Efficient Load Balancing Selection Strategy for Adaptive NoC Routers. NoCArc@MICRO 2014: 31-36 - 2013
- [c4]John Jose, Bhawna Nayak, Damarla Kranthi Kumar, Madhu Mutyam:
DeBAR: deflection based adaptive router with minimal buffering. DATE 2013: 1583-1588 - [c3]Bhawna Nayak, John Jose, Madhu Mutyam:
SLIDER: Smart Late Injection DEflection Router for mesh NoCs. ICCD 2013: 377-383 - 2012
- [c2]John Jose, K. V. Mahathi, J. Shiva Shankar, Madhu Mutyam:
TRACKER: A low overhead adaptive NoC router with load balancing selection strategy. ICCAD 2012: 564-568 - 2011
- [c1]John Jose, J. Shiva Shankar, K. V. Mahathi, Damarla Kranthi Kumar, Madhu Mutyam:
BOFAR: buffer occupancy factor based adaptive router for mesh NoCs. NoCArc@MICRO 2011: 23-28
Coauthor Index
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