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ORCIDMikaël Briday
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2020 – today
- 2024
[c19]Hugo Reymond
, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou:
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems. CGO 2024: 258-269- [c18]Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou:
EarlyBird: Energy belongs to those who wake up early. RTCSA 2024: 1-10 - 2023
- [j4]Rémi Parrot, Mikaël Briday, Olivier H. Roux:
Design and verification of pipelined circuits with Timed Petri Nets. Discret. Event Dyn. Syst. 33(1): 1-24 (2023) - [j3]Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux:
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems. Discret. Event Dyn. Syst. 33(1): 63-93 (2023) - [c17]Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon:
Securing a RISC-V architecture: A dynamic approach. DATE 2023: 1-5 - 2021
- [c16]Rémi Parrot, Mikaël Briday, Olivier H. Roux:
Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design. Petri Nets 2021: 55-75 - [c15]Rémi Parrot, Mikaël Briday, Olivier H. Roux:
Pipeline Optimization using a Cost Extension of Timed Petri Nets. ARITH 2021: 37-44 - [c14]Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange:
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds. Audio Mostly Conference 2021: 147-155
2010 – 2019
- 2018
- [c13]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday:
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. AHS 2018: 249-256 - [c12]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection. EDCC 2018: 25-32 - 2017
- [c11]Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou:
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. VECoS 2017: 64-78 - 2016
- [c10]Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware runtime verification of embedded software in SoPC. SIES 2016: 171-176 - [c9]Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou:
BEST: a Binary Executable Slicing Tool. WCET 2016: 7:1-7:10 - 2014
- [c8]Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux:
Reactive embedded device driver synthesis using logical timed models. SIMULTECH 2014: 163-169 - [c7]Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet:
Improving processor hardware compiled cycle accurate simulation using program abstraction. SimuTools 2014: 186-194 - 2013
- [c6]Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux:
Device driver synthesis for embedded systems. ETFA 2013: 1-8 - 2012
- [j2]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet:
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. J. Syst. Archit. 58(8): 318-337 (2012) - 2011
- [j1]Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem:
An Architecture Description Language for Embedded Hardware Platforms. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 44 (2011) - [c5]Jean-Luc Béchennec, Mikaël Briday, Valere Alibert:
Extending Harmless architecture description language for embedded real-time systems validation. SIES 2011: 223-231 - 2010
- [c4]Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif:
ViPER: a lightweight approach to the simulation of distributed and embedded software. SimuTools 2010: 74
2000 – 2009
- 2009
- [c3]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton:
Instruction set simulator generation using HARMLESS, a new hardware architecture description language. SimuTools 2009: 24 - 2008
- [c2]Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton:
Simulator generation using an automaton based pipeline model for timing analysis. IMCSIT 2008: 657-664 - 2006
- [c1]Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet:
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. ETFA 2006: 62-69
Coauthor Index
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last updated on 2024-10-17 20:32 CEST by the dblp team
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