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ORCIDAndreas Hansson 0001
Person information
- affiliation: Axelera AI, Eindhoven, The Netherlands
- affiliation (former): ARM Ltd., Cambridge, UK
- affiliation (former): University of Twente, Enschede, The Netherlands
- affiliation (PhD 2009): Eindhoven University of Technology, The Netherlands
- affiliation (former): Lund University, Sweden
Other persons with the same name
- Andreas Hansson 0002 — Huawei Technologies, Kista, Sweden
- Andreas Hansson 0003 — University of Skövde, Sweden
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2020 – today
- 2020
[i2]Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian
, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian:
The gem5 Simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
2010 – 2019
- 2018
- [i1]Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn:
Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact. CoRR abs/1803.07613 (2018) - 2017
- [j10]Christian Weis, Abdul Mutaal, Omar Naji, Matthias Jung, Andreas Hansson, Norbert Wehn:
DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. Int. J. Parallel Program. 45(6): 1566-1591 (2017) - [j9]Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup Das, Sheng Yang, Bashir M. Al-Hashimi, Geoff V. Merrett:
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 106-119 (2017) - [c23]Radhika Jagtap, Matthias Jung, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn:
Integrating DRAM power-down modes in gem5 and quantifying their impact. MEMSYS 2017: 86-95 - 2016
- [c22]Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson:
Elastic traces for fast and accurate system performance exploration. ISPASS 2016: 147-148 - [c21]Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi:
Thermally-aware composite run-time CPU power models. PATMOS 2016: 17-24 - [c20]Radhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung, Norbert Wehn:
Exploring system performance using elastic traces: Fast, accurate and portable. SAMOS 2016: 96-105 - 2015
- [c19]Anup Das, Matthew J. Walker, Andreas Hansson, Bashir M. Al-Hashimi, Geoff V. Merrett:
Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones. ISLPED 2015: 165-170 - [c18]René de Jong, Andreas Hansson:
A full-system approach to analyze the impact of next-generation mobile flash storage. ISPASS 2015: 235-244 - [c17]Christian Weis, Matthias Jung, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson:
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. ISVLSI 2015: 609-614 - [c16]Omar Naji, Christian Weis, Matthias Jung, Norbert Wehn, Andreas Hansson:
A high-level DRAM timing, power and area exploration tool. SAMOS 2015: 149-156 - 2014
- [c15]Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas F. Wenisch, Aniruddha N. Udipi:
Simulating DRAM controllers for future system architecture exploration. ISPASS 2014: 201-210 - 2013
- [c14]Vasileios Spiliopoulos, Akash Bagdia, Andreas Hansson, Peter Aldworth, Stefanos Kaxiras:
Introducing DVFS-Management in a Full-System Simulator. MASCOTS 2013: 535-545 - [c13]Sascha Bischoff, Andreas Hansson, Bashir M. Al-Hashimi:
Applying of Quality of Experience to system optimisation. PATMOS 2013: 91-98 - 2011
- [j8]Andreas Hansson, Kees Goossens:
A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications. Des. Autom. Embed. Syst. 15(2): 159-190 (2011) - [j7]Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens:
Design and implementation of an operating system for composable processor sharing. Microprocess. Microsystems 35(2): 246-260 (2011) - [p1]Benny Akesson, Anca Mariana Molnos, Andreas Hansson, Jude Angelo Ambrose, Kees Goossens:
Composability and Predictability for Independent Application Development, Verification, and Execution. Multiprocessor System-on-Chip 2011: 25-56 - 2010
- [c12]Kees Goossens, Andreas Hansson:
The aethereal network on chip after ten years: goals, evolution, lessons, and future. DAC 2010: 306-311 - [c11]Andrew Nelson, Andreas Hansson, Henk Corporaal, Kees Goossens:
Conservative application-level performance analysis through simulation of MPSoCs. ESTIMedia 2010: 51-60
2000 – 2009
- 2009
- [j6]Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij:
Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis. IET Comput. Digit. Tech. 3(5): 398-412 (2009) - [j5]Andreas Hansson, Benny Akesson, Jef L. van Meerbergen:
Multi-processor programming in the embedded system curriculum. SIGBED Rev. 6(1): 9 (2009) - [j4]Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken:
CoMPSoC: A template for composable and predictable multi-processor system on chips. ACM Trans. Design Autom. Electr. Syst. 14(1): 2:1-2:24 (2009) - [c10]Andreas Hansson, Kees Goossens:
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. CODES+ISSS 2009: 99-108 - [c9]Andreas Hansson, Mahesh Subburaman, Kees Goossens:
Aelite: A flit-synchronous Network on Chip with composable and predictable services. DATE 2009: 250-255 - [c8]Benny Akesson, Andreas Hansson, Kees Goossens:
Composable Resource Sharing Based on Latency-Rate Servers. DSD 2009: 547-555 - 2008
- [j3]Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten:
A monitoring-aware network-on-chip design flow. J. Syst. Archit. 54(3-4): 397-410 (2008) - [c7]Andreas Hansson, Maarten Wiggers, Arno Moonen, Kees Goossens, Marco Bekooij:
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip. NOCS 2008: 211-212 - 2007
- [j2]Andreas Hansson, Kees Goossens, Andrei Radulescu:
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic. VLSI Design 2007: 68432:1-68432:16 (2007) - [j1]Andreas Hansson, Kees Goossens, Andrei Radulescu:
Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip. VLSI Design 2007: 95859:1-95859:10 (2007) - [c6]Andreas Hansson, Martijn Coenen, Kees Goossens:
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. CODES+ISSS 2007: 149-154 - [c5]Akash Kumar, Andreas Hansson, Jos Huisken, Henk Corporaal:
Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip. DATE 2007: 117-122 - [c4]Andreas Hansson, Martijn Coenen, Kees Goossens:
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. DATE 2007: 954-959 - [c3]Andreas Hansson, Kees Goossens:
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases. NOCS 2007: 233-242 - 2006
- [c2]Calin Ciordas, Andreas Hansson, Kees Goossens, Twan Basten:
A Monitoring-Aware Network-on-Chip Design Flow. DSD 2006: 97-106 - 2005
- [c1]Andreas Hansson, Kees Goossens, Andrei Radulescu:
A unified approach to constrained mapping and routing on network-on-chip architectures. CODES+ISSS 2005: 75-80
Coauthor Index
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