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2020 – today
- 2024
[j3]Arvind Raghavan
, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen:
A Fully Integrated 1 GHz 8A Imax Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3016-3028 (2024)- 2022
- [c3]Christopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas:
A IMax |max, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS. ISSCC 2022: 1-3
2010 – 2019
- 2015
- [j2]Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer:
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33(3): 10:1-10:32 (2015) - 2014
- [j1]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34(3): 120-137 (2014) - 2013
- [c2]Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA 2013: 142-153
2000 – 2009
- 2002
- [c1]Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton:
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6
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last updated on 2024-07-20 20:33 CEST by the dblp team
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