default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 3
Volume 3, Number 1, January 2010
- Antonio Roldao Lopes, George A. Constantinides:
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices. 1:1-1:19 - David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor Davenport, Steve Poole:
Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer with Application. 2:1-2:31 - Saar Drimer, Tim Güneysu
, Christof Paar:
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs. 3:1-3:27 - Shannon Koh, Oliver Diessel:
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration. 4:1-4:36 - John Curreri, Seth Koehler, Alan D. George, Brian Holland, Rafael García:
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing. 5:1-5:23
Volume 3, Number 2, May 2010
- John Bodily, Brent E. Nelson, Zhaoyi Wei, Dah-Jye Lee, Jeff Chase:
A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs. 6:1-6:22 - Konstantinos Papadopoulos, Ioannis Papaefstathiou:
Titan-R: A Multigigabit Reconfigurable Combined Compression/Decompression Unit. 7:1-7:25 - Benoît Badrignans, David Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres:
SARFUM: Security Architecture for Remote FPGA Update and Monitoring. 8:1-8:29 - Sang-Kyung Yoo, Deniz Karakoyunlu, Berk Birand, Berk Sunar:
Improving the Robustness of Ring Oscillator TRNGs. 9:1-9:30 - Ted Huffmire, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine, Brett Brotherton, Gang Wang, Timothy Sherwood, Ryan Kastner:
Security Primitives for Reconfigurable Hardware-Based Systems. 10:1-10:35
Volume 3, Number 3, September 2010
- K. Scott Hemmert, Keith D. Underwood:
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs. 11:1-11:30 - Ahmad Sghaier, Shawki Areibi, Robert D. Dony:
Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms. 12:1-12:28 - Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. 13:1-13:21 - James Moscola, Ron K. Cytron, Young H. Cho:
Hardware-Accelerated RNA Secondary-Structure Alignment. 14:1-14:44 - Yosi Ben-Asher, Danny Meisler, Nadav Rotem:
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs. 15:1-15:19 - Xiaojun Wang, Miriam Leeser:
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware. 16:1-16:34 - Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert, Michael Hussmann, Michael Thies, Uwe Kastens:
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. 17:1-17:25 - Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt:
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. 18:1-18:30
Volume 3, Number 4, November 2010
- Jason Williams, Chris Massie, Alan D. George, Justin Richardson, Kunal Gosrani, Herman Lam:
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration. 19:1-19:29 - Miaoqing Huang, Vikram K. Narayana, Harald Simmler, Olivier Serres, Tarek A. El-Ghazawi:
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing. 20:1-20:25 - Kentaro Sano, Luzhou Wang, Yoshiaki Hatsuda, Takanori Iizuka, Satoru Yamamoto:
FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods. 21:1-21:35 - Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam:
MPI as a Programming Model for High-Performance Reconfigurable Computers. 22:1-22:29 - Matt Chiu, Martin C. Herbordt:
Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems. 23:1-23:37 - Alessio Montone, Marco D. Santambrogio, Donatella Sciuto, Seda Ogrenci Memik:
Placement and Floorplanning in Dynamically Reconfigurable FPGAs. 24:1-24:34 - Casey Reardon, Eric Grobelny, Alan D. George, Gongyu Wang:
A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems. 25:1-25:29 - Xiang Tian, Khaled Benkrid:
High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU. 26:1-26:22
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-05-06 21:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
