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ORCID36th SoCC 2023: Santa Clara, CA, USA
- Jürgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin:
36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023. IEEE 2023, ISBN 979-8-3503-0011-6 - Ben Perach, Ronny Ronen, Shahar Kvatinsky:
Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. 1-6 - Sena Busra Yengec-Tasdemir, Fahad Siddiqui
, Sakir Sezer, Henry Hui, Kieran McLaughlin, Balmukund Sonigara:
A Comparative Analysis of Security Patterns for Enhancing Security in Safety-Critical Systems. 1-6 - Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura:
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks. 1-6 - Mohamed El-Hadedy, Russell Hua, Shahzman Saqib, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala:
BLTESTI: Benchmarking Lightweight TinyJAMBU on Embedded Systems for Trusted IoT. 1-6 - Henry Hui, Kieran McLaughlin, Fahad Siddiqui, Sakir Sezer, Sena Yengec Tasdemir, Balmukund Sonigara:
A Runtime Security Monitoring Architecture for Embedded Hypervisors. 1-6 - Tim Hotfilter, Julian Höfer, Philipp Merz, Fabian Kreß, Fabian Kempf, Tanja Harbaum, Jürgen Becker:
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency. 1-6 - Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura:
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction. 1-6 - Prabuddha Chakraborty, Tasneem Suha, Swarup Bhunia:
Hardware Specification Aware Timing Side Channel Security Analysis. 1-6 - Zhuoran Li, Dan Zhao:
μThingNet: Leveraging Fine-Grained Power Analysis towards A Robust Zero-Day Defender. 1-6 - Bijay Raj Paudel, Haibo Wang, Spyros Tragoudas, Omkar Rijal:
High Precision Winner-Take-All Circuit for Neural Networks. 1-6 - Ashish Mahanta, Haibo Wang:
PRIDES: A Power Rising Descending Signature for Improving IoT Security. 1-6 - Kasim Tasdemir, Rafiullah Khan, Fahad Siddiqui, Sakir Sezer, Fatih Kurugollu, Alperen Bolat:
An Investigation of Machine Learning Algorithms for High-bandwidth SQL Injection Detection Utilising BlueField-3 DPU Technology. 1-6 - Zheyu Yan, Yifan Qin, Xiaobo Sharon Hu, Yiyu Shi:
On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators. 1-6 - Renya Makimoto, Takashi Imagawa, Hiroyuki Ochi:
Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. 1-6 - Jaeha Lee, Seungmin Lee, Hyeongkyu Kim, Taejun Yoo, Minjung Park, Seiseung Yoon:
Pin Accessibility Improvement with Hit-Point Distribution Metrics for Sub-4nm Standard Cell. 1-6 - Mehdi Saberi, Zahra Ghasemzadeh, Alexandre Schmid:
A Delay and Power Efficient Voltage Level Shifter with Low Leakage Power. 1-5 - Babak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks. 1-6 - Yuan-Tai Lin, Chin-Yu Sun, TingTing Hwang:
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties. 1-6 - Min-Su Kim, Jin-Soo Park, Chung-Hee Kim, Bai-Sun Kong:
DCVS Level Shifter for Clock Path. 1-2 - Zheming Jin, Jeffrey S. Vetter:
Experience Migrating OpenCL to SYCL: A Case Study on Searches for Potential Off-Target Sites of Cas9 RNA-Guided Endonucleases on AMD GPUs. 1-6 - Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. 1-6 - Yu-Cheng Wu, Chi-Tse Huang, An-Yeu Andy Wu:
DEA-NIMC: Dynamic Energy-Aware Policy for Near/In-Memory Computing Hybrid Architecture. 1-6 - Dima Al Saleh, Yousef Safari, Fahad Rahman Amik, Boris Vaisband:
P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs. 1-6 - Kevin Wohnrade, Darius Grantz, Martin Zeller, Jens Benndorf:
An Automotive Vision SoC Platform from IVI to AD Level 4. 1-2 - Danushka Senarathna, Spyros Tragoudas:
Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation. 1-6 - Reon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima:
Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing. 1-6 - Abrar Abdurrob, Emre Salman, Jack Lombardi:
Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators. 1-6 - Guan-Wei Wu, Cheng-Yang Chang, An-Yeu Andy Wu:
DE-C3: Dynamic Energy-Aware Compression for Computing-In-Memory-Based Convolutional Neural Network Acceleration. 1-6 - Yuta Yachi, Masashi Tawada, Nozomu Togawa:
A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. 1-6 - Hamza Saleem, Lubna Shah, Abdur Rehman, Hassan Saif, Rashad Ramzan:
AC-Logic Family for Smart Dust and IoT Applications. 1-5 - Markus Graber, Klaus Hofmann:
An Enhanced 1440 Coupled CMOS Oscillator Network to Solve Combinatorial Optimization Problems. 1-6 - Jaewan Yang, Taewhan Kim:
Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling. 1-6 - Sriharini Krishnakumar, Inna Partin-Vaisband:
Vertical Power Delivery for Emerging Packaging and Integration Platforms - Power Conversion and Distribution. 1-6 - Sonia Akter, Kasem Khalil, Magdy A. Bayoumi:
Hardware Security in the Internet of Things: A Survey. 1-6 - Kevin Mika, Florian Porrmann, Nils Kucza, René Griessl, Jens Hagemeyer:
RECS: A Scalable Platform for Heterogeneous Computing. 1-6 - Rashad Ramzan, Azam Beg, Syed Arsalan Jawed, Muhammad Aaquib Shahbaz, Muhammad Junaid:
Quadrature RF-Only Logic Family for Single-Chip Self-Powered Transceivers. 1-5 - Yerzhan Mustafa, Selçuk Köse:
Covert Communication Attacks in Chiplet-based 2.5-D Integration Systems. 1-5 - Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara:
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. 1-6 - Pragya Laad:
18FD-SOI: Case Study at Arm. 1-2 - Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura:
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery. 1-6 - Madhava Sarma Vemuri, Umamaheswara Rao Tida:
FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration. 1-6 - Mutsumi Kimura, Shu Shiomi, Norito Komai, Etsuko Iwagi, Tomoharu Yokoyama, Yuma Ishisaki, Tokiyoshi Matsuda, Hidenori Kawanishi:
Thin-Film Memristors and Memcapacitors for 3D Integration of Neuromorphic Systems. 1-6 - Moamen El-Masry, Sohaib Anees, Robert Weigel:
Spiking Neural Networks Design-Space Exploration Platform Supporting Online and Offline Learning. 1-5 - Chen Li, Suwen Song, Jing Tian, Zhongfeng Wang, Çetin Kaya Koç:
An Efficient Hardware Design for Fast Implementation of HQC. 1-6 - Yimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma, Xinfei Guo, Mircea Stan:
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores. 1-6 - Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems. 1-6 - Brian Pachideh, Christian Zielke, Sven Nitzsche, Jürgen Becker:
Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware. 1-6 - Yunpeng Yao, Yirong Kan, Guangxian Zhu, Renyuan Zhang:
A Low Latency Spiking Neural Network with Improved Temporal Dynamics. 1-6 - Christie Agbalessi, Mark A. Indovina:
CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs. 1-6 - Zekun Wang, Shinichi Nishizawa, Shinji Kimura:
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding. 1-6 - Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors. 1-6 - Daniel Hofman, Mario Brcic, Mihael Kovac, Tim Hotfilter, Jürgen Becker, Dominik Reinhardt, Sorin Mihai Grigorescu, R. Stevens, T. T. Vo:
European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System. 1-6 - Alperen Bolat, Fahad Siddiqui, Sakir Sezer, Kasim Tasdemir, Rafiullah Khan:
Investigation of Communication Overhead of SoC Lookaside Accelerators. 1-6 - Yugal Kishore Maheshwari, Manoj Sachdev:
VLFF - A Very Low-power Flip-flop with only Two Clock Transistors. 1-6 - Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe:
An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit. 1-5 - Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou:
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. 1-6 - Shahzad Haider, Ke Hu, Song Chen:
Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch. 1-5 - Yiyang Xu, Dahong Qian:
ZodiacMSM: A Heterogeneous, Multi-node and Scalable Multi-Scalar Multiplication System for Zero Knowledge Proof Acceleration. 1-6 - Andres Ayes, Eby G. Friedman:
Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks. 1-5 - Balmukund Sonigara, Sakir Sezer, Fahad Siddiqui, Raphael Weber, Konstantinos Antonopoulos, Christos Panagiotou, Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Sena Yengec Tasdemir, Henry Hui, Kieran McLaughlin:
XANDAR: Verification & Validation Approach for Safety-critical Systems. 1-6
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