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ORCIDNANOARCH 2019: Qingdao, China
- IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2019, Qingdao, China, July 17-19, 2019. IEEE 2019, ISBN 978-1-7281-5520-3
- Yue Zhang, Jiang Nan, Guanda Wang, Xueying Zhang, Youguang Zhang, Weisheng Zhao:
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions. 1-2 - Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao:
A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. 1-6 - Behnoush Attarimashalkoubeh, Yusuf Leblebici:
Novel 3D architecture of 1S1R. 1-2 - Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao:
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM. 1-6 - Tingting Zhang
, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders. 1-6 - Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao:
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction. 1-6 - Chengjun Wu, Weiwei Shan, Jiaming Xu:
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience. 1-6 - Tao Wang, Weiwei Shan:
An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing. 1-6 - Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler:
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing. 1-6 - Dongning Ma, Xun Jiao:
Detecting and Bypassing Trivial Computations in Convolutional Neural Networks. 1-6 - Lei Xie, Hao Cai, Jun Yang:
REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing. 1-4 - Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang:
A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. 1-6 - Jianxun Yang, Leibo Liu, Jin Zhang, Shaojun Wei, Shouyi Yin:
An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks. 1-6 - Roberto Carboni, E. Vernocchi, M. Siddik, J. Harms, A. Lyle, G. Sandhu, Daniele Ielmini:
A compact model of stochastic switching in STT magnetic RAM for memory and computing. 1-6 - Juejian Wu, Mingyang Gu, Hongtao Zhong, Yunsong Tao, Fei Qiao, Huazhong Yang, Xueqing Li:
Enabling New Computing Paradigms with Emerging Symmetric-Access Memories. 1-6 - Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner:
Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. 1-6 - Rashid Ali, You Wang, Zhengyi Hou, Haoyuan Ma, Youguang Zhang, Weisheng Zhao:
Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes. 1-6 - Chengzhi Wang, Deming Zhang, Lang Zeng, Kaili Zhang, Youguang Zhang, Weisheng Zhao:
Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque. 1-6 - Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui:
Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme. 1-6 - Shaahin Angizi, Deliang Fan:
Deep Neural Network Acceleration in Non-Volatile Memory: A Digital Approach. 1-6 - Wang Kang, He Zhang, Weisheng Zhao:
Spintronic Memories: From Memory to Computing-in-Memory. 1-2 - Vasileios G. Ntinas, Antonio Rubio, Georgios Ch. Sirakoulis, Rosana Rodríguez, Montserrat Nafría:
Experimental Investigation of Memristance Enhancement. 1-2 - Tifenn Hirtzlin, Bogdan Penkovsky, Jacques-Olivier Klein, Nicolas Locatelli, Adrien F. Vincent, Marc Bocquet, Jean-Michel Portal, Damien Querlioz:
Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction. 1-5 - He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana:
Graphene Nanoribbon-based Synapses with Versatile Plasticity. 1-6 - Sandeep Krishna Thirumala, Arnab Raha, Vijaykrishnan Narayanan, Vijay Raghunathan, Sumeet Kumar Gupta:
Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors. 1-6 - Nicholas Jao, Srivatsa Srivinasa, Akshay Krishna Ramanathan, Minhwan Kim, John Sampson, Vijaykrishnan Narayanan:
Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads. 1-6 - Xiaolong Ma, Geng Yuan, Sheng Lin, Zhengang Li, Hao Sun, Yanzhi Wang:
ResNet Can Be Pruned 60×: Introducing Network Purification and Unused Path Removal (P-RM) after Weight Pruning. 1-2 - Alexandru Paler, Robert Basmadjian:
Clifford Gate Optimisation and T Gate Scheduling: Using Queueing Models for Topological Assemblies. 1-5 - Md Arif Iqbal, Naveen Kumar Macha, Bhavana Tejaswini Repalle, Mostafizur Rahman:
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs. 1-6 - Konstantinos Rallis, Panagiotis Dimitrakis, Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Antonio Rubio:
Effect of Lattice Defects on the Transport Properties of Graphene Nanoribbon. 1-2 - Panagiotis Karakolis, Pascal Normand, Panagiotis Dimitrakis, L. Sygelou, Vasileios G. Ntinas, Iosif-Angelos Fyrigos, Ioannis Karafyllidis, George Ch. Sirakoulis:
Plasma Modified Silicon Nitride Resistive Switching Memories. 1-2
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