default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID47th MICRO 2014: Cambridge, United Kingdom
- 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-6998-2
Session 1A: Stacked DRAM
- Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi:
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. 1-12 - Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim:
Transparent Hardware Management of Stacked DRAM as Part of Memory. 13-24 - Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi:
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache. 25-37 - Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan:
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. 38-50 - Prashant J. Nair, David A. Roberts, Moinuddin K. Qureshi:
Citadel: Efficiently Protecting Stacked Memory from Large Granularity Failures. 51-62
Session 1B: GPGPU and Data Parallel Architectures
- HyoukJoong Lee, Kevin J. Brown, Arvind K. Sujeeth, Tiark Rompf, Kunle Olukotun:
Locality-Aware Mapping of Nested Parallel Patterns on GPUs. 63-74 - Ji Yun Kim, Christopher Batten:
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists. 75-87 - Guoyang Chen, Bo Wu, Dong Li, Xipeng Shen
:
PORPLE: An Extensible Optimizer for Portable Data Placement on GPU. 88-100 - Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic:
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures. 101-113 - Onur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das:
Managing GPU Concurrency in Heterogeneous Architectures. 114-126
Session 2A: Memory Systems, Scheduling, and Optimization
- Joshua San Miguel, Mario Badr, Natalie D. Enright Jerger:
Load Value Approximation. 127-139 - Jeffrey R. Diamond, Donald S. Fussell, Stephen W. Keckler:
Arbitrary Modulus Indexing. 140-152 - Jishen Zhao, Onur Mutlu, Yuan Xie:
FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems. 153-165 - Praveen Yedlapalli, Nachiappan Chidambaram Nachiappan, Niranjan Soundararajan, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das:
Short-Circuiting Memory Traffic in Handheld Platforms. 166-177 - Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift:
Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks. 178-189
Session 2B: Security
- Dmitry Evtyushkin, Jesse Elwell, Meltem Ozsoy, Dmitry V. Ponomarev, Nael B. Abu-Ghazaleh, Ryan Riley:
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution. 190-202 - Fangfei Liu, Ruby B. Lee:
Random Fill Cache Architecture. 203-215 - Jie Chen, Guru Venkataramani:
CC-Hunter: Uncovering Covert Timing Channels on Shared Processor Hardware. 216-228 - Erdem Aktas, Furat Afram, Kanad Ghose:
Continuous, Low Overhead, Run-Time Validation of Program Executions. 229-241 - Robert Locke Callan, Alenka G. Zajic, Milos Prvulovic:
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events. 242-254
Session 3A: Methodology, Modeling, and Tools
- Jaewon Lee, Hanhwi Jang, Jangwoo Kim:
RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks. 255-267 - Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee:
GPUMech: GPU Performance Modeling Technique Based on Interval Analysis. 268-279 - Derek Lockhart, Gary Zibrat, Christopher Batten:
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. 280-292
Session 3B: Reliability and Fault Tolerance
- Mark Wilkening, Vilas Sridharan, Si Li, Fritz Previlon, Sudhanva Gurumurthi, David R. Kaeli:
Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults. 293-305 - Anys Bacha, Radu Teodorescu:
Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors. 306-318 - Daya Shanker Khudia, Scott A. Mahlke:
Harnessing Soft Computations for Low-Budget Fault Tolerance. 319-330
Session 4A: TLB and Cache Optimization
- Somayeh Sardashti, André Seznec, David A. Wood:
Skewed Compressed Caches. 331-342 - Xuhao Chen, Li-Wen Chang, Christopher I. Rodrigues, Jie Lv, Zhiying Wang, Wen-mei W. Hwu:
Adaptive Cache Management for Energy-Efficient GPU Computing. 343-355 - Ruisheng Wang, Lizhong Chen:
Futility Scaling: High-Associativity Cache Partitioning. 356-367
Session 4B: Managing Voltage and Time
- Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose, Timothy J. Slegel, Gerard Salem, Sean M. Carey, Richard F. Rizzolo, Thomas Strach:
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities. 368-380 - Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B. Apsel, Christopher Batten:
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks. 381-393 - Jeongseob Ahn, Chang Hyun Park, Jaehyuk Huh:
Micro-Sliced Virtual Processors to Hide the Effect of Discontinuous CPU Availability for Consolidated Systems. 394-405
Session 5A: Energy-Efficient Computation
- Yunqi Zhang, Michael A. Laurenzano, Jason Mars, Lingjia Tang:
SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers. 406-418 - Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Front-End Execution Architecture for High Energy Efficiency. 419-431 - Michael McKeown, Jonathan Balkind, David Wentzlaff:
Execution Drafting: Energy Efficiency through Computation Deduplication. 432-444 - Bo Su, Junli Gu, Li Shen, Wei Huang, Joseph L. Greathouse, Zhiying Wang:
PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration. 445-457
Session 5B: Interconnects
- Natalie D. Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh:
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? 458-470 - Supreet Jeloka, Reetuparna Das, Ronald G. Dreslinski, Trevor N. Mudge, David T. Blaauw:
Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration. 471-483 - Gwangsun Kim, Minseok Lee, Jiyun Jeong, John Kim:
Multi-GPU System Design with Memory Networks. 484-495 - Haofan Yang, Jyoti Tripathi, Natalie D. Enright Jerger, Dan Gibson:
Dodec: Random-Link, Low-Radix On-Chip Networks. 496-508
Session 6A: Branch Prediction and Prefetching
- Jorge Albericio, Joshua San Miguel, Natalie D. Enright Jerger, Andreas Moshovos:
Wormhole: Wisely Predicting Multidimensional Branches. 509-520 - Dibakar Gope, Mikko H. Lipasti:
Bias-Free Branch Predictor. 521-532 - Adi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion:
Loop-Aware Memory Prefetching Using Code Block Working Sets. 533-544 - Stavros Volos, Javier Picorel, Babak Falsafi, Boris Grot:
BuMP: Bulk Memory Access Prediction and Streaming. 545-557
Session 6B: Compilation and Code Generation
- Michael A. Laurenzano, Yunqi Zhang, Lingjia Tang, Jason Mars:
Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers. 558-570 - Wei Ding, Diana R. Guttman, Mahmut T. Kandemir:
Compiler Support for Optimizing Memory Bank-Level Parallelism. 571-582 - Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten:
Architectural Specialization for Inter-Iteration Loop Dependence Patterns. 583-595 - Qing Yi, Qian Wang, Huimin Cui:
Specializing Compiler Optimizations through Programmable Composition for Dense Matrix Computations. 596-608
Session 7: Best Paper Nominees
- Yunji Chen, Tao Luo, Shaoli Liu, Shijin Zhang, Liqiang He, Jia Wang, Ling Li, Tianshi Chen, Zhiwei Xu, Ninghui Sun, Olivier Temam:
DaDianNao: A Machine-Learning Supercomputer. 609-622 - David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez:
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. 623-634 - Daniel Lustig, Michael Pellauer, Margaret Martonosi:
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. 635-646 - Ankit Sethia, Scott A. Mahlke:
Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution. 647-658 - Linhai Song, Min Feng, Nishkam Ravi, Yi Yang, Srimat T. Chakradhar:
COMP: Compiler Optimizations for Manycore Processors. 659-671
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-11 20:32 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
