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ORCID35th MICRO 2002: Istanbul, Turkey
- Erik R. Altman, Kemal Ebcioglu, Scott A. Mahlke, B. Ramakrishna Rau, Sanjay J. Patel:
Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002. ACM/IEEE Computer Society 2002, ISBN 0-7695-1859-1
Superscalar Design
- José F. Martínez
, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas:
Cherry: checkpointed early resource recycling in out-of-order microprocessors. 3-14 - J. Adam Butts, Gurindar S. Sohi:
Characterizing and predicting value degree of use. 15-26 - Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, Bryan Black:
Hierarchical Scheduling Windows. 27-36 - Vlad Petric, Anne Bracy, Amir Roth:
Three extensions to register integration. 37-47
Multithreading I
- Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta:
Instruction fetch deferral using static slack. 51-61 - Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen:
Pointer cache assisted prefetching. 62-73 - Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt:
Microarchitectural support for precomputation microthreads. 74-84 - Craig B. Zilles, Gurindar S. Sohi:
Master/slave speculative parallelization. 85-96
Compiler scheduling
- Josep Llosa, Stefan M. Freudenberger:
Reduced code size modulo scheduling in the absence of hardware support. 99-110 - Walter Lee, Diego Puppin, Shane Swenson, Saman P. Amarasinghe:
Convergent scheduling. 111-122 - Enric Gibert, F. Jesús Sánchez, Antonio González:
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. 123-133 - Youfeng Wu, Ryan N. Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang:
Compiler managed micro-cache bypassing for high performance EPIC processors. 134-145
Register file and memory system design
- Jesús Corbal, Roger Espasa, Mateo Valero:
Three-dimensional memory vectorization for high bandwidth media memory systems. 149-160 - Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai:
Dynamic addressing memory arrays with physical locality. 161-170 - Il Park, Michael D. Powell, T. N. Vijaykumar:
Reducing register ports for higher speed and lower energy. 171-182
Energy efficient memory systems
- Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen:
Generating physical addresses directly for saving instruction TLB energy. 185-196 - Jun Yang, Rajiv Gupta:
Energy efficient frequent value data cache design. 197-207 - Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Compiler-directed instruction cache leakage optimization. 208-218 - Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge:
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. 219-230
Compilation and run-time systems
- Ronald D. Barnes, Erik M. Nystrom, Matthew C. Merten, Wen-mei W. Hwu:
Vacuum packing: extracting hardware-detected program phases for post-link optimization. 233-244 - Changqing Fu, Kent D. Wilken:
A faster optimal register allocator. 245-256 - Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Joseph A. Fisher:
DELI: a new run-time control point. 257-268
Simulation and architecture evaluation
- Manish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, David I. August:
Microarchitectural exploration with Liberty. 271-282 - Christoforos E. Kozyrakis, David A. Patterson:
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks. 283-293 - Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik:
Orion: a power-performance simulator for interconnection networks. 294-305 - Chris J. Thompson, Sahngyun Hahn, Mark Oskin:
Using modern graphics architectures for general-purpose computing: a framework and analysis. 306-317
Energy aware design
- Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman:
Managing static leakage energy in microprocessor functional units. 321-332 - Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma:
Optimizing pipelines for power and performance. 333-344 - K. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir:
Power protocol: reducing power dissipation on off-chip data buses. 345-355 - Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott:
Dynamic frequency and voltage control for a multiple clock domain microarchitecture. 356-367
Superscalar microarchitecture
- Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero:
Fetching instruction streams. 371-382 - André Seznec, Eric Toullec, Olivier Rochecouste:
Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. 383-394 - Gabriel H. Loh:
Exploiting data-width locality to increase superscalar execution bandwidth. 395-405
Multithreading II
- Dirk Grunwald, Soraya Ghiasi:
Microarchitectural denial of service: insuring microarchitectural fairness. 409-418 - Rakesh Kumar, Dean M. Tullsen:
Compiling for instruction cache performance on a multithreaded architecture. 419-429 - Amir Roth, Gurindar S. Sohi:
A quantitative framework for automated pre-execution thread selection. 430-441
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