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ORCID23rd MICRO 1990: Orlando, Florida, USA
- Christos A. Papachristou, Vicki H. Allan:
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990. ACM/IEEE 1990, ISBN 0-89791-413-9 - Michael J. Flynn:
Instruction sets and their implementations. 1-6 - Marco Danelutto, Marco Vanneschi:
VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors. 7-16 - Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu:
A software pipelining based VLIW architecture and optimizing compiler. 17-27 - Rajiv Gupta:
A fine-grained MIMD architecture based upon register channels. 28-37 - Soo-Mook Moon, Scott D. Carson, Ashok K. Agrawala:
Hardware implementation of a general multi-way jump mechanism. 38-45 - Reese B. Jones, Vicki H. Allan:
Software pipelining: a comparison and improvement. 46-56 - Toshio Nakatani, Kemal Ebcioglu:
Using a lookahead window in a compaction-based parallelizing compiler. 57-68 - Alexandru Nicolau, Roni Potasman:
Realistic scheduling: compaction for pipelined architectures. 69-79 - Alessandro De Gloria, Paolo Faraboschi:
An evaluation system for application specific architectures. 80-89 - Johannes M. Mulder, Robert J. Portier, A. Srivastava:
A framework for high-speed controller design. 90-96 - Paul Kenyon, Prathima Agrawal, Sharad C. Seth:
High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. 97-106 - Philip H. Sweany, Steven J. Beaty:
Post-compaction register assignment in a retargetable compiler. 107-116 - Steven J. Beaty, L. Darrell Whitley, Gearold Johnson:
Motivation and framework for using genetic algorithms for microcode compaction. 117-124 - S. ShouHan Wang, Augustus K. Uht:
Ideograph/Ideogram: framework/hardware for eager evaluation. 125-134 - Jong-Jiann Shieh, Christos A. Papachristou:
An instruction reoderer for pipelined computers. 135-142 - Feipei Lai, Hung-Chang Lee, Chun-Luh Lee:
Optimization on instruction reorganization. 143-148 - David Binger, David Knapp:
Automatic synthesis of a dual-PLA controller with a counter. 149-157 - Forrest Brewer
, Barry M. Pangrle, Andrew Seawright:
Interconnection synthesis with geometric constraints. 158-165 - Farhad Mavaddat, M. Mahmood, Mantis H. M. Cheng:
An application of L systems to local microcode synthesis. 166-175 - Tsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin:
The selection of optimal cache lines for microprocessor-based controllers. 183-192 - Arvin Park, Matthew K. Farrens:
Address compression through base register caching. 193-199 - Feipei Lai, Chyuan-Yow Wu, Tai-Ming Parng:
A memory management unit and cache controller for the MARS system. 200-208 - Matthew K. Farrens, Andrew R. Pleszkun:
An evaluation of functional unit lengths for single-chip processors. 209-215 - Lawrence Rauchwerger, P. Michael Farmwald:
A multiple floating point coprocessor architecture. 216-222 - Reuven Bakalash, Zhong Xu:
A barrel shift microsystem for parallel processing. 223-229 - Beverly Gocal:
PRISM architecture: parallel and pipeline features. 230-236 - Leonardo Campanale, Mario De Blasi, Anna Gentile, F. Greco:
Topologies for the parallel backtracking Prolog engine. 237-242 - Christian Iseli, Eduardo Sanchez:
A high-level microprogrammed processor. 244-251 - Djahida Smati, Jerry P.-C. Hwang, Christos A. Papachristou:
SMDSS - a structured microcode development and simulation system. 252-259 - Suntae Hwang, Rochit Rajsuman, Yashwant K. Malaiya:
On the testing of microprogrammed processor. 260-266 - C. Hwa Chang, Hammad K. Azzam:
A weighted technique for programmable logic devices minimization. 267-274 - Liwen Shih:
Microprogramming heritage of RISC design. 275-280 - Sunil R. Das, Amiya Nayak:
A survey on bit dimension optimization strategies of microprograms. 281-291 - Monica Alderighi, Giacomo R. Sechi:
A model of a microprogrammed functional-oriented computing unit. 292-298
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