default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC-Asia 2022: Taipei, Taiwan
- IEEE International Test Conference in Asia, ITC-Asia 2022, Taipei, Taiwan, August 24-26, 2022. IEEE 2022, ISBN 978-1-6654-5523-7
- Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase:
Fault Resilience Techniques for Flash Memory of DNN Accelerators. 1-6 - Yu-Cheng Yang, Jin-Fu Li:
Fault Modeling and Testing of RRAM-based Computing-In Memories. 7-12 - Duo-Yao Kang, Shiou-Ning Lin, Kuen-Jong Lee:
Diagnosing Transition Delay Faults under Scan-Based Logic Array. 13-18 - Ya-Chi Cheng, Pai-Yu Tan
, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. 19-24 - Shian-Yu Lin, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. 25-30 - Yueling Jenny Zeng, Min Jian Yang, Li-C. Wang:
Wafer Map Pattern Analytics Driven By Natural Language Queries. 31-36 - Jiun-Cheng Tsai, Aaron C.-W. Liang, Charles H.-P. Wen:
Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability. 37-42 - Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara:
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. 43-48 - Jia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang:
Test Response Compaction for Software-Based Self-Test. 49-54 - Jin-Fu Li:
Testing and Reliability of Computing-In Memories: Solutions and Challenges. 55-60 - Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui:
Structured Test Development Approach for Computation-in-Memory Architectures. 61-66 - Leon Brackmann, Atousa Jafari, Christopher Bengel, Mahta Mayahinia, Rainer Waser, Dirk J. Wouters, Stephan Menzel, Mehdi B. Tahoori:
A failure analysis framework of ReRAM In-Memory Logic operations. 67-72 - Aibin Yan, Shukai Song, Jixiang Zhang, Jie Cui, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard:
Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS. 73-78 - Aobo Cui, Dongrong Zhang, Qiang Ren, Donglin Su:
A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC. 79-84 - Yi-Ying Chen, Soon-Jyh Chang:
A Physically Unclonable Function Embedded in a SAR ADC. 85-89 - Hideyuki Ichihara, Naruki Itoh, Tomoo Inoue:
An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application. 90-95 - Juan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Ernesto Sánchez, Matteo Sonza Reorda:
Evaluating the impact of Permanent Faults in a GPU running a Deep Neural Network. 96-101
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-05-02 23:42 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
