default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 2024: San Diego, CA, USA
- IEEE International Test Conference, ITC 2024, San Diego, CA, USA, November 3-8, 2024. IEEE 2024, ISBN 979-8-3315-2013-7
- Daniel Adjei, Emmanuel Nti Darko, Degang Chen:
A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits. 1-5 - Lars Hedrich, Inga Abel, Jaafar Mejri, Vladimir A. Zivkovic:
Identifying Undetectable Defects Using Equivalence Checking. 6-10 - Soham Roy, Vishwani D. Agrawal:
Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults. 11-15 - Abhishek Kumar Mishra, Suman Kumar, Anush Niranjan Lingamoorthy, Anup Das, Nagarajan Kandasamy:
Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification. 16-20 - Brian Pajak, Pankaj Pant, Vidya Neerkundar:
From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel. 21-25 - Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. 26-30 - Irith Pomeranz:
Functionally-Possible Gate-Exhaustive Bridging Faults. 31-35 - Anlin Liu, Tianyao Lu, Yuhao Xi, Yangfan Liu, Peng Liu:
Enhancing Functional Verification with Dynamic Instruction Generation by Exploiting Processor Runtime States. 36-40 - Stephan Eggersglüß, Andreas Glowatz:
A Cell-aware Transistor State Stress Model and its Application for Quality Measurement. 41-45 - Zhe Zhang, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi B. Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects. 46-50 - Sandeep Kumar Goel, Moiz Khan, Ankita Patidar, Frank Lee, Vuong Nguyen, Bharath Shankaranarayanan, Doo Kim, Manish Arora:
Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. 51-55 - Seongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi, Chanyeol Park, Sunyong Park, Woonphil Yang:
Probe Card Ground Noise Canceling Circuit. 56-60 - Hiroyuki Iwata, Mahmoud AbdAlwahab, Ron Press, Ohki Sugiura:
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs. 61-65 - Krishna Pramod Madabhushi, Trevor LaBanz, Sudip Dandnaik, Eslam Hag:
Scalable BIST for Linearity Testing of Sigma-Delta Modulators. 66-70 - Aleksa Deric, Kyle Mitard, Shahin Tajik, Daniel E. Holcomb:
Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques. 71-75 - Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant. 76-80 - Ali Nezhadi, Mahta Mayahinia, Mehdi B. Tahoori:
Cross-Layer Reliability Evaluation of In-Memory Similarity Computation. 81-85 - Pratishtha Agnihotri, Priyank Kalla, Steve Blair:
Design-for-Test for Silicon Photonic Circuits. 86-90 - Changhao Wang, Sicong Yuan, Hanzhi Xun, Chaobo Li, Mottaqiallah Taouil, Moritz Fieback, Danyang Chen, Xiuyan Li, Lin Wang, Riccardo Cantoro, Chujun Yin, Said Hamdioui:
Defects, Fault Modeling, and Test Development Framework for FeFETs. 91-95 - Dhruv Thapar, Arjun Chaudhuri, Kai Ni, Krishnendu Chakrabarty:
Defect Analysis for FeFETs using a Compact Model. 96-100 - Leon Li, Alex Orailoglu:
Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation. 101-105 - Hossein Pourmehrani, Javad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash, Naghmeh Karimi:
FAT-RABBIT: Fault-Aware Training towards Robustness AgainstBit-flip Based Attacks in Deep Neural Networks. 106-110 - Min Jian Yang, Yueling Jenny Zeng, Li-C. Wang:
WM-Graph: Graph-Based Approach for Wafermap Analytics. 111-120 - C. W. Lin, P. C. Tsao, Ross Lee, Khim Koh, Y. J. Ting, Jennifer Hsiao, C. T. Lai, T. H. Lee:
Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence. 121-128 - Mehul D. Shroff, Nguyen Nguyen, Kiran Sunny Thota:
A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction. 129-138 - Wu-Tung Cheng, Manish Sharma, Xin Yang, Artur Stelmach, Szczepan Urban, Jakub Janicki, Preston McWithey:
Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage. 139-148 - Yi-Chun Huang, Pei-Yun Lin, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee:
Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips. 149-156 - Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Delay Monitoring Under Different PVT Corners for Test and Functional Operation. 157-166 - Jonathan Gaudet, Jan Burchard, Matthias Kampmann, Jean-François Côté, Tim Callahan, Hung Ho Chai, Ivy Ee Hsia Lim, Lori Schramm, Olga Przybysz, Marta Stepniewska, Sascha Ochsenknecht, Michal Olejarz, Martin Keim:
High-Bandwidth IJTAG over SSN. 167-176 - Ashish Reddy Bommana, Farshad Firouzi, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory*. 177-186 - Yen-Wei Li, Cheng-Yun Hsieh, Meng-Chen Wu, James Chien-Mo Li:
qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors. 187-196 - Corrado De Sio, Luca Sterpone:
Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip. 197-206 - Geancarlo Abich, Ricardo Augusto da Luz Reis, Luciano Ost:
Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge Devices. 207-216 - Ishaan Bassi, Sule Ozev:
Electrical Stimulus Based Calibration of MEMS Accelerometer. 217-225 - Matthew Nigh, John M. Carulli, Yiorgos Makris:
Generation and Quality Evaluation of Synthetic Process Control Monitoring Data. 226-232 - Xuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji:
Safety-Guided Test Generation for Structural Faults. 233-242 - Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty:
E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry. 243-252 - Suriyaprakash Natarajan, Chaitali S. Oak, Vijay Kakollu, Nipun Chaplot, Soham Roy, Apurva Lonkar, Gerardo J. Perfecto Reyes:
Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor. 253-260 - Chi Lai, Shi-Yu Huang:
Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test. 261-269 - Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel:
A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation. 270-279 - Jaehoon Lee, Hyeonuk Son, Seohyun Kang, Dahyun Kang, Dongkwan Han, Jongsin Yun, Artur Pogiel, Etienne Racine, Krzysztof Jurga, Lori Schramm, Martin Keim:
Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies. 280-285 - Xinyang Zhao, Baohua Wang, Yin Zhang, Weiming Zhang, Xiaotian Ding, Yu Huang:
Diagnosis of Defects on Global Signals. 286-292 - Yunkun Lin, Mingye Li, Sandeep Gupta:
Predictive Testing for Aging in SRAMs and Mitigation. 293-302 - Galib Ibne Haidar, Md Sami Ul Islam Sami, Jingbo Zhou, Kimia Zamiri Azar, Mark M. Tehranipoor, Farimah Farahmandi:
SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits. 303-312 - Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Test Data Encryption with a New Stream Cipher. 313-322 - Dipali Jain, Guangwei Zhao, Rajesh Datta, Kaveh Shamsi:
Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation. 323-332 - Saurabh Upadhyay, Ahmet Tokuz:
Scan SerDes* for Multi-die Packages. 333-338 - Stephen Sunter, Krzysztof Jurga:
Digital Scan and ATPG for Analog Circuits. 339-347 - Ilya Wagner, Pankaj Pant, Arani Sinha:
Functional State Extraction using Scan DFT. 348-353 - Sina Bakhtavari Mamaghani, Jongsin Yun, Martin Keim, Mehdi B. Tahoori:
MBIST-based MRAM defect screening for safety-critical applications. 354-363 - Sicong Yuan, Hanzhi Xun, Woojin Kim, Siddharth Rao, Erik Jan Marinissen, Sebastien Couet, Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui:
Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? 364-373 - Hanzhi Xun, Moritz Fieback, Mohammad Amin Yaldagard, Sicong Yuan, Erbing Hua, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui:
Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs. 374-383 - Albert Au, Michal Kçpinski, Makary Orczyk, Artur Pogiel:
Power-Aware Test Scheduling for Memory BIST. 384-390 - Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer:
Deterministic In-Fleet Scan Test for a Cloud Computing Platform. 391-399 - Kunal Jain Mangilal, Mahmut Yilmaz, Vishal Agarwal, Shantanu Sarangi, Kaushik Narayanun:
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. 400-406 - Alan S.-M. Liu, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh:
LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets. 407-416 - Pierre Scaramuzza, Thomas Kern, Matteo Coppetta, Alessandro Grossi, Rudolf Ullmann:
A graph-based algorithm for NVM address decoders testing. 417-425 - Suhasini Komarraju, Mohamed Mejri, Abhijit Chatterjee, Suriyaprakash Natarajan, Prashant Goteti:
TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering. 426-435 - Varun Thukral, Chen He, Rebecca Chen, Letian Zhang, Romuald Roucou, Michiel van Soestbergen, Jeroen J. M. Zaal, Rene Rongen, Willem D. van Driel, G. Q. Zhang:
AI-Enabled Board Level Vibration Testing: Unveiling The Physics of Degradation. 436-444 - E. Aderholz, Q. Atol, B. Baptist, R. Holzner, R. Ignacio, V. Kamanuri, A. Kun, K. Ma, B. Mariacher, O. Pfabigan, A. Przybilla, D. Samardzic, F. Schlagbauer, M. Schleicher, J. P. Valiente, E. Vargas, K. Vinod, O. Zikulnig:
Virtual Test Development Using Pre-Silicon Verification Environment. 445-450 - Sandeep Kumar Goel, Ankita Patidar, Moiz Khan, Frank Lee, Anshuman Chandra, Martin Keim, Naim Lemar, Jonathan Gaudet, Quoc Phan, Vidya Neerkundar:
Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. 451-459
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-13 19:00 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
