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ORCID26th DAC 1989: Las Vegas, Nevada, USA
- Donald E. Thomas:
Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989. ACM Press 1989 - Pierre G. Paulin, John P. Knight:
Scheduling and Binding Algorithms for High-Level Synthesis. 1-6 - Miodrag Potkonjak, Jan M. Rabaey:
A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs. 7-12 - P. Sadayappan, V. Visvanathan:
Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. 13-18 - Antony P.-C. Ng, V. Visvanathan:
A Framework for Scheduling Multi-Rate Circuit Simulation. 19-24 - Patrick Odent, Luc J. M. Claesen, Hugo De Man:
Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. 25-30 - G. D. Adams, Carlo H. Séquin:
Template Style Considerations for Sea-of-Gates Layout Generation. 31-36 - Ichiang Lin, David Hung-Chang Du, Steve H.-C. Yen:
Gate Matrix Layout Synthesis with Two-Dimensional Folding. 37-42 - David Marple:
Transistor Size Optimization in the Tailor Layout System. 43-48 - Osamu Karatsu:
VLSI Design Language Standardization Effort in Japan. 50-55 - Rajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker:
Experience with ADAM Synthesis System. 56-61 - Elizabeth D. Lagnese, Donald E. Thomas:
Architectural Partitioning for System Level Design. 62-67 - M. Balakrishnan, Peter Marwedel:
Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. 68-74 - Sally A. Hayati, Alice C. Parker:
Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions. 75-80 - Larry Soulé, Anoop Gupta:
Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation. 81-86 - Zhicheng Wang, Peter M. Maurer:
Scheduling High-Level Blocks for Functional Simulation. 87-90 - Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
:
Massively Parallel Switch-Level Simulation: A Feasibility Study. 91-97 - Moon-Jung Chung, Y. Chung:
Data Parallel Simulation Using Time-Warp on the Connection Machine. 98-103 - M. T. Trick, Stephen W. Director:
LASSIE: Structure to Layout for Behavioral Synthesis Tools. 104-109 - Wing K. Luk, Alvar A. Dean:
Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout. 110-115 - B. Lokanathan, Edwin Kinnen:
Performance optimized floor planning by graph planarization. 116-121 - Mitsuru Igusa, Mark Beardslee, Alberto L. Sangiovanni-Vincentelli:
ORCA a Sea-of-Gates Place and Route System. 122-127 - Michael C. McFarland:
The Social Implications of Computerization: Making the Technology Humane. 129-134 - William P. Birmingham, Anurag P. Gupta, Daniel P. Siewiorek:
The MICON System for Computer Design. 135-140 - Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt:
GABRIEL: A Design Environment for Programmable DSPs. 141-146 - Anshul Kumar, Shashi Kumar, P. Kulshreshtha, Sudipto Ghose:
Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions. 147-154 - P. Groenveld:
On Global Wire Ordering for Macro-Cell Routing. 155-160 - Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong:
A New Approach to the Rectilinear Steiner Tree Problem. 161-166 - Naveed A. Sherwani, Jitender S. Deogun:
A New Heuristic for Single Row Routing Problems. 167-172 - A. Salz, Mark Horowitz:
IRSIM: An Incremental MOS Switch-Level Simulator. 173-178 - David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh:
Automatic Generation of Behavioral Models from Switch-Level Descriptions. 179-184 - Kensaburo Alfredo Tamura:
Locating Functional Errors in Logic Circuits. 185-191 - Anthony I. Wasserman:
CASE Environments for Design Automation. 193-196 - James Daniell, Stephen W. Director:
An Object Oriented Approach to CAD Tool Control within a Design Framework. 197-202 - Claudia S. Frydman, Norbert Giambiasi, M. Gatumel, P. Bayle:
DeBuMA: Description, Building and Management of Applications. 203-208 - E. C. VanHorn, Roy R. Rezac:
Experience with D-BUS Architecture for a Design Automation Framework. 209-214 - TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
Multi-Level Logic Synthesis Using Communication Complexity. 215-220 - Patrick C. McGeer, Robert K. Brayton:
Efficient Prime Factorization of Logic Expressions. 221-225 - Alan J. Coppola:
New Methods in the Analysis of Logic Minimization Data and Algorithms. 226-231 - C. C. Chen, S.-L. Chow:
The Layout Synthesizer: An Automatic Netlist-to-Layout System. 232-238 - Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo:
GENAC: An Automatic Cell Synthesis Tool. 239-244 - Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili:
A Module Generator for Optimized CMOS Buffers. 245-250 - Marianne Winslett, David W. Knapp, Keith Hall, Gio Wiederhold:
Use of Change Coordination in an Information-rich Design Environment. 252-257 - Alexandros Biliris:
Database Support for Evolving Design Objects. 258-263 - Mário J. Silva, David Gedye, Randy H. Katz, Richard Newton:
Protection and Versioning for OCT. 264-269 - Srinivas Devadas:
Approaches to Multi-level Sequential Logic Synthesis. 270-276 - Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Multi-level Logic Simplification Using Don't Cares and Filters. 277-282 - Rajeev Goré, Kotagiri Ramamohanarao:
Automatic Synthesis of Boolean Equations Using Programmable Array Logic. 283-289 - Hyunchul Shin, Chi-Yuan Lo:
An Efficient Two-Dimensional Layout Compaction Algorithm. 290-295 - Johannes Waterkamp, Ralner Wicke, Rainer Brück, Michael Reinhardt, Georg Schrammeck:
Technology Tracking of Non Manhattan VLSI Layout. 296-301 - Chi-Yuan Lo:
Automatic Tub Region Generation for Symbolic Layout Compaction. 302-306 - Kurt Keutzer:
Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. 308-313 - Srinivas Devadas:
General Decomposition of Sequential Machines: Relationships to State Assignment. 314-320 - Gabriele Saucier, Christopher Duff, Franck Poirot:
State Assignment Using a New Embedding Method Based on an Intersecting Cube Theory. 321-326 - Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations. 327-332 - Pierre G. Paulin:
Horizontal Partitioning of PLA-based Finite State Machines. 333-338 - Srinivas Patil, Prithviraj Banerjee:
A Parallel Branch and Bound Algorithm for Test Generation. 339-343 - Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim:
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. 345-350 - C. Thomas Glover, M. Ray Mercer:
A Deterministic Approach to Adjacency Testing for Delay Faults. 351-356 - Michael H. Schulz, Franz Fink, Karl Fuchs:
Parallel Pattern Fault Simulation of Path Delay Faults. 357-363 - Somchai Prasitjutrakul, William J. Kubitz:
Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement. 364-369 - Michael A. B. Jackson, Ernest S. Kuh:
Performance-driven Placement of Cell Based IC's. 370-375 - Alexander Herrigel, Wolfgang Fichtner:
An Analytic Optimization Technique for Placement of Macro-Cells. 376-381 - Sarma Sastry, Jen-I Pi:
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems. 382-387 - R. H. Bruce, W. P. Meuli, J. Ho:
Multi Chip Modules. 389-393 - Bryan Preas, Massoud Pedram, Don Curry:
Automatic Layout of Silicon-on-Silicon Hybrid Packages. 394-399 - Ran Libeskind-Hadas, C. L. Liu:
Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. 400-405 - Jih-Shyr Yih, Pinaki Mazumder:
A Neural Network Design for Circuit Partitioning. 406-411 - Meng-Lin Yu:
A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD. 412-417 - Kyeongsoon Cho, Randal E. Bryant:
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation. 418-423 - Wu-Tung Cheng, Meng-Lin Yu:
Differential Fault Simulation - a Fast Method Using Minimal Memory. 424-428 - F. E. Norrod:
An Automatic Test Generation Algorithm for Hardware Description Languages. 429-434 - Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin:
VVDS: A Verification/Diagnosis System for VHDL. 435-440 - Lothar Nowak, Peter Marwedel:
Verification of Hardware Descriptions by Retargetable Code Generation. 441-447 - Cyrus Bamji, Jonathan Allen:
GRASP: A Grammar-based Schematic Parser. 448-453 - Andrzej J. Strojwas:
Design for Manufacturability and Yield. 454-459 - Aangelo C. Hung, Philip M. Reddy, Paul J. Hammer:
MIOS: A Flexible System for PCB Manufacturing. 460-465 - William D. Smith, David A. Duff, Martin Dragomirecky, James L. Caldwell, Michael J. Hartman, Jeffrey R. Jasica, Manuel A. d'Abreu:
FACE Core Environment: The Model and Its Application in CAE/CAD Tool Development. 466-471 - Klaus D. Müller-Glaser, Jürgen Bortolazzi:
An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules. 472-477 - Júlio S. Aude, Hilary J. Kahn:
Representation and Use of Design Rules within a Technology Adaptable CAD System. 478-484 - Pak K. Chan, Kevin Karplus:
Computing Signal Delay in General RC Networks by Tree/Link Partitioning. 485-490 - Serge Gaiotti, Michel R. Dagenais, Nicholas C. Rumin:
Worst-case Delay Estimation of Transistor Groups. 491-495 - Nagisa Ishiura, Mizuki Takahashi, Shuzo Yajima:
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits. 497-502 - Charles R. Bonapace, Chi-Yuan Lo:
An O(nlogm) Algorithm for VLSI Design Rule Checking. 503-507 - Nils Hedenstierna, Kjell O. Jeppson:
The Use of Inverse Layout Trees for Hierarchical Design Rule Checking. 508-512 - Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man:
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. 513-518 - Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai:
MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. 519-524 - Wen-Ben Jone, Christos A. Papachristou:
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. 525-534 - Wen-Ben Jone, Christos A. Papachristou, M. Pereira:
A Scheme for Overlaying Concurrent Testing of VLSI Circuits. 531-536 - O. A. Buset, Mohamed I. Elmasry:
ACE: A Hierarchical Graphical Interface for Architectual Synthesis. 537-542 - Dorothy E. Setliff, Rob A. Rutenbar:
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. 543-548 - Martin Dragomirecky, Ephraim P. Glinert, Jeffrey R. Jasica, David A. Duff, William D. Smith, Manuel A. d'Abreu:
High-Level Graphical User Interface Management in the FACE Synthesis Environment. 549-554 - David Hung-Chang Du, S. H. Yen, Subbarao Ghanta:
On the General False Path Problem in Timing Analysis. 555-560 - Patrick C. McGeer, Robert K. Brayton:
Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. 561-567 - S. Perremans, Luc J. M. Claesen, Hugo De Man:
Static Timing Analysis of Dynamically Sensitizable Paths. 568-573 - Carol V. Gura, Jacob A. Abraham:
Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. 574-577 - Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer:
Efficient Final Placement Based on Nets-as-Points. 578-581 - Marwan A. Jabri, David J. Skellern:
PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System. 582-585 - D. F. Wong, P. S. Sakhamuri:
Efficient Floorplan Area Optimization. 586-589 - Jeff S. Sargent, Prithviraj Banerjee:
A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. 590-593 - John D. Gabbe, P. A. Subrahmanyam:
A Note on Clustering Modules for Floorplanning. 594-597 - David Knapp:
An Interactive Tool for Register-level Structure Optimization. 598-601 - Nam Sung Woo, Hyunchul Shin:
A Technology-adaptive Allocation of Functional Units and Connections. 602-605 - Joseph Lis, Daniel Gajski:
VHDL Synthesis Using Structured Modeling. 606-609 - William P. Birmingham, Daniel P. Siewiorek:
Capturing Designer Expertise the CGEN System. 610-613 - David L. Hwang, Thomas L. Wernimont, W. Kent Fuchs:
Evaluation of a Reconfigurable Architecture for Digital Beamforming Using the OODRA Workbench. 614-617 - Michael Rumsey, John Sackett:
An ASIC Methodology for Mixed Analog-Digital Simulation. 618-621 - R. F. Milsom, K. J. Scott, S. G. Clark, J. C. McEntegart, S. Ahmed, F. N. Soper:
FACET: A CAE System for RF Analogue Simulation Including Layout. 622-625 - Zhiping Yu, Weijian Zhao, Zhilian Yang, Y. Edmund Lien:
A Novel Algorithm for Improving Convergence Behavior of Circuit Simulators. 626-629 - Andrew T. Yang, S. M. Kang:
iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development. 630-633 - Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer:
AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. 634-637 - Kaushik Roy, Jacob A. Abraham:
A Novel Approach to Accurate Timing Verification Using RTL Descriptions. 638-641 - A. K. George:
Evaluating Hardware Models in DIGITAL's System Simulation Environment. 642-644 - Prathima Agrawal, Raffi Tutundjian, William J. Dally:
Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. 645-648 - S. H. Yen, David Hung-Chang Du, Subbarao Ghanta:
Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis. 649-654 - Nicholas Weiner, Alberto L. Sangiovanni-Vincentelli:
Timing Analysis in a Logic Synthesis Environment. 655-661 - Jacques Wenin, Johan Verhasselt, Marc Van Camp, Jean Leonard, Pierre Guebels:
Rule-based VLSI Verification System Constrained by Layout Parasitics. 662-667 - Jacques Benkoski, Andrzej J. Strojwas:
Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. 668-673 - Narasimha B. Bhat, S. K. Nandy:
Special Purpose Architecture for Accelerating Bitmap DRC. 674-677 - N. P. van der Meijs, Arjan J. van Genderen:
An Efficient Finite Element Method for Submicron IC Capacitance Extraction. 678-681 - Kuang-Wei Chiang:
Resistance Extraction and Resistance Calculation in GOALIE? 682-685 - Leon Stok, G. P. Koster:
From Network to Artwork. 686-689 - Wen-Jeng Lue, Lawrence P. McNamee:
Extracting Schematic-like Information from CMOS Circuit Net-lists. 690-693 - I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man:
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. 694-697 - Mary Jane Irwin, Robert Michael Owens:
A Comparison of Four Two-dimensional Gate Matrix Layout Tools. 698-701 - Knut M. Just, Werner L. Schiele, Thomas Krüger:
Plowing: Modifying Cells and Routing 45: 9D - Layouts. 702-705 - T. Ghewala:
CrossCheck: A Cell Based VLSI Testability Solution. 706-709 - V. G. Hemmady, Sudhakar M. Reddy:
On the Repair of Redundant RAMs. 710-713 - Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya:
CMOS Stuck-open Fault Detection Using Single Test Patterns. 714-717 - Bulent I. Dervisoglu, M. A. Keil:
ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation. 718-721 - Utpal J. Davé, Janak H. Patel:
A Functional-Level Test Generation Methodology Using Two-level Representations. 722-725 - Jhing-Fa Wang, Tah-Yuan Kuo, Jau-Yien Lee:
A New Approach to Derive Robust Sets for Stuck-open Faults in CMOS Combinational Logic Circuits. 726-729 - Weiwei Mao, Michael D. Ciletti:
A Simplified Six-waveform Type Method for Delay Fault Testing. 730-733 - Vinod Narayanan, Vijay Pitchumani:
A Massively Parallel Algorithm for Fault Simulation on the Connection Machine. 734-737 - A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick M. Dewilde:
A New Model for the High Level Description and Simulation of VLSI Networks. 738-741 - Walling R. Cyre:
Toward Synthesis from English Descriptions. 742-745 - Steven S. Leung:
Behavioral Modeling of Transmission Gates in VHDL. 746-749 - Paul R. Jordan, Ronald D. Williams:
COMP: A VHDL Composition System. 750-753 - Nikil D. Dutt, Daniel Gajski:
Designer Controlled Behavioral Synthesis. 754-757 - J. Blanks:
Partitioning by Probability Condensation. 758-761 - Andrew B. Kahng:
Fast Hypergraph Partition. 762-766 - Youssef Saab, Vasant B. Rao:
An Evolution-Based Approach to Partitioning ASIC Systems. 767-770 - Gopalakrishnan Vijayan:
Min-cost Partitioning on a Tree Structure and Applications. 771-774 - Thang Nguyen Bui, C. Heigham, Curt Jones, Frank Thomson Leighton:
Improving the Performance of the Kernighan-Lin and Simulated Annealing Graph Bisection Algorithms. 775-778 - Shantanu Ganguly, Vijay Pitchumani:
Compaction of a Routed Channel on the Connection Machine. 779-782 - Rajiv Dutta, Malgorzata Marek-Sadowska:
Automatic Sizing of Power/Ground (P/G) Networks in VLSI. 783-786 - S. Chowdhury:
Optimum Design of Reliable IC Power Networks Having General Graph Topologies. 787-790 - Yasuyuki Fujihara, Yutaka Sekiyama, Yasuo Ishibashi, Masao Yanaka:
DYNAJUST: An Efficient Automatic Routing Technique Optimizing Delay Conditions. 791-794 - Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap, J. A. Gandhi:
DTR: A Defect-Tolerant Routing Algorithm. 795-798 - Khe-Sing The, D. F. Wong, Jason Cong:
VIA Minimization by Layout Modification. 799-802 - Wanhao Li, Hart Switzer:
A Unified Data Exchange Environment Based on EDIF. 803-806 - Julia Miller, Klaus Gröning, Gerhard Schulz, Charles White:
The Object-Oriented Integration Methodology of the Cadlab Work Station Design Environment. 807-810 - Paul Kollaritsch, Steve Lusky, Doug Matzke, Derek Smith, Paul Stanford:
A Unified Design Representation Can Work. 811-813 - Ernst Siepmann, Gerhard Zimmermann:
An Object-Oriented Datamodel for the VLSI Design System PLAYOUT. 814-817 - Mark Roberts:
CEDIF: A Data Driven EDIF Reader. 818-821 - Larry G. Jones:
Fast Online/Offline Netlist Compilation of Hierarchical Schematics. 822-825 - Gert Goossens, Joos Vandewalle, Hugo De Man:
Loop Optimization in Register-Transfer Scheduling for DSP-Systems. 826-831 - Hiroto Yasuura, Nagisa Ishiura:
Semantics of a Hardware Design Language for Japanese Standardization. 836-839
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