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ORCID14th DAC 1977: New Orleans, Louisiana, USA
- Judith G. Brinsfield, Stephen A. Szygenda, David W. Hightower:
Proceedings of the 14th Design Automation Conference, DAC '77, New Orleans, Louisiana, USA, June 20-22, 1977. ACM 1977 - Ikuo Nishioka, Takuji Kurimoto, Hisao Nishida:
A minicomputerized automatic layout system for two-layer printed wiring boards. 1-11 - Ivan Dobes:
A multi-contouring algorithm. 12 - W. G. Cage, Robert J. Smith:
A rectangle-probe router for multilayer P.C. boards. 13-22 - Prathima Agrawal, Melvin A. Breuer:
Some theoretical aspects of algorithmic routing. 23-31 - William R. Heller, W. F. Michail, Wilm E. Donath:
Prediction of wiring space requirements for LSI. 32-42 - Donald P. Peterson:
Computer/interactive cleanup of non-gridded PWB's after automatic routing. 43-57 - Predrag G. Kovijanic:
A new look at test generation and verification. 58-63 - R. H. Somaia:
An automated simultaneous probing system for testing complex logic assemblies 'the bed of nails system'. 64-67 - Klaus Pfeuffer:
Computer aided test pattern generation for digital processors. 68-77 - Akihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu:
Automatic test generation for large digital circuits. 78-83 - Richard E. Strebendt:
Heuristic enhancement of an algorithmic test generator. 84-87 - Thomas J. Snethen:
Simulator-oriented fault test generator. 88-93 - Patricia Fulton:
Tools for map graphics. 94-100 - Mark Domaszewicz:
Flight test analysis of missile control systems. 101-108 - Richard S. Hall:
MIDAS an on-line real time material system. 109-111 - Ned L. Brown:
Using a computer aided graphics system to help design and draft automotive components. 112-117 - James J. Strunge:
Fault modeling in a hierarchical simulator. 118-127 - Miron Abramovici, Melvin A. Breuer, K. Kumar:
Concurrent fault simulation and functional level modeling. 128-137 - Y. Eric Cho, A. J. Korenjak, David E. Stockton:
Floss: An approach to automated layout for high-volume designs. 138-141 - Albert E. Ruehli, Peter K. Wolff Sr., Gerald Goertzel:
Analytical power/timing optimization technique for digital system. 142-146 - Barbara J. Agule, Jean Davies Lesser, Albert E. Ruehli, Peter K. Wolff Sr.:
An experimental system for power/timing optimization of LSI chips. 147-152 - Konrad W. Koller, Ulrich Lauther:
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits. 153-157 - Nigel R. Crocker, R. W. McGuffin, A. Micklethwaite:
Automatic ECL LSI design. 158-167 - K. Bedard, Serge Fournier, B. Shastry, U. Stockburger:
A production PCB layout system on a minicomputer. 168-173 - Teresa de Pedro, Ricardo García:
DOCIL: An automatic system for printed circuit board (PCB) designing. A board description language and an algorithm to connect a set of points. 174-181 - Andrew J. Matthews:
A human engineered PCB design system. 182-186 - Franz J. Rammig:
A concept for the editing of hardware resulting in an automatic hardware-editor. 187-193 - I. L. Morris, J. McNulty, R. Gee:
Simulation of large communications networks using SPIN. 194-204 - Yacoub M. El-Ziq, Stephen Y. H. Su:
Logic design automation of diagnosable MOS combinational logic networks. 205-215 - Bengt Magnhagen:
Practical experiences from signal probability simulation of digital designs. 216-219 - Ajoy K. Bose, Stephen A. Szygenda:
Detection of static and dynamic hazards in logic nets. 220-224 - James R. Armstrong, Garry W. Woodruff:
Simulation techniques for microprocessors. 225-229 - Donald M. Schuler, Roger K. Cleghorn:
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories. 230-238 - Elliott E. Dudnik:
Uncertainty and optimization in the design of building subsystems. 239-243 - Michael Kennedy:
Symbols, graphics and architectural education: The pagan experience. 244-253 - Donald E. Bergeson, Robert Babbin:
An affordable approach to an architectural computer system. 254-264 - Barry Jackson:
Evolution of a spatial allocation system: Allocate. 265 - Edward F. Smith:
THE SITE MACHINE Computer-aided instruction in architectural education. 266-274 - Robert Simpson Frew:
Computer aided design in North American Schools of Architecture. 275-276 - Gordon A. Gebert:
Computer-aided design and practice in city college school of architecture. 277-278 - Eric Teicholz:
Computer-aided architectural design. 279 - Kenneth E. Tanaka, Donald E. Berseson:
Department of architecture university of illinois. 280 - Michael Kennedy:
Computer aided design college of architecture University of Kentucky. 281 - Robert J. Hogan:
A second chance at automation as a design tool. 282 - Robert Simpson Frew:
Yale school of architecture. 283 - Melvin A. Breuer:
A class of min-cut placement algorithms. 284-290 - K. H. Khokhani, Arvind M. Patel:
The chip layout problem: A placement procedure for lsi. 291-297 - K. A. Chen, Michael Feuer, K. H. Khokhani, Ning Nan, S. Schmidt:
The chip layout problem: An automatic wiring procedure. 298-302 - Henry S. Baird:
Fast algorithms for LSI artwork analysis. 303-311 - R. M. Allgair, D. S. Evans:
A comprehensive approach to a connectivity audit, or a fruitful comparison of apples and oranges. 312-321 - Kenji Yoshida, Takashi Mitsuhashi, Yasuo Nakada, Toshiaki Chiba, Kiyoshi Ogita, Shinji Nakatsuka:
A layout checking system for large scale integrated circuits. 322-330 - Justin E. Harlow III:
The open shop interactive mask design operation at harris semiconductor. 331-335 - Max Amon:
Automatic optical design with accos v program. 336-340 - A. Bobas, J. Valihora:
A design automation system for printed circuit board assemblies. 341-350 - Chester W. Waldvogel:
Computer designed multilayer hybrid substrate using thick film technology. 351-353 - Howard E. Krohn:
Design verification of large scientific computers. 354-361 - William A. Noon:
A Design Verification and Logic Validation System. 362-368 - Carlo J. Evangelisti, Gerald Goertzel, Hillel Ofek:
Designing with LCD: language for computer design. 369-376 - William M. van Cleemput:
An hierarchical language for the structural description of digital systems. 377-385 - Robert P. Larsen:
Cost effective layout digitizing and mask pen plotting of custom microelectronic devices. 386-390 - Richard C. Jaffe, Joseph P. Young:
Automating analog circuit diagrams using a list processing language. 391-395 - Hedayat Markus Bayegan:
CASS: Computer aided schematic system. 396-404 - Carol A. Linden:
Manipulation of design data. 405-410 - Donald E. Thomas, Daniel P. Siewiorek:
Measuring designer performance to verify design automation systems. 411-418 - Frank E. Swiatek:
A design automation system for telephone electronic switching system. 419-424 - Denis K. Carley:
SWESS - the middle system of a design automation network. 425-430 - Michael E. Walsh:
SPIDER - a Computer Aided Manufacturing Network. 431-436 - R. W. Srch:
PIRAMED project an integrated CAD/CAM system development. 437-444 - J. Robert Heath, Bill D. Carroll, Terry T. Cwik:
CDL - A tool for concurrent hardware and software development. 445-449 - Freddie M. Christley:
Thick film substrate (Micropackage) design utilizing interactive Computer Aided Design systems. 450-459 - M. Correia, F. B. Petrini:
Introduction to an LSI test system. 460-461 - Edward B. Eichelberger, Thomas W. Williams:
A logic design structure for LSI testability. 462-468 - Humbert C. Godoy, G. B. Franklin, Peter S. Bottorff:
Automatic checking of logic design structures For compliance with testability ground rules. 469-478 - Peter S. Bottorff, Richard E. France, N. H. Garges, E. J. Orosz:
Test generation for large logic networks. 479-485 - E. R. Hsieh, Robert A. Rasmussen, L. J. Vidunas, W. T. Davis:
Delay test generation. 486-491 - Thomas M. Storey, J. W. Barry:
Delay test simulation. 492-494 - Robert J. Smith:
Software engineering techniques in design automation - a tutorial. 495-507
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