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ORCID16th ARC 2020: Toledo, Spain
- Fernando Rincón
, Jesús Barba, Hayden Kwok-Hay So, Pedro C. Diniz, Julián Caba:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed]. Lecture Notes in Computer Science 12083, Springer 2020, ISBN 978-3-030-44533-1
Design Methods and Tools
- Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk:
Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. 3-13 - Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi:
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. 14-29 - Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Optimising Operator Sets for Analytical Database Processing on FPGAs. 30-44 - Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre:
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. 45-60 - Bruno Ferres, Olivier Muller, Frédéric Rousseau:
Chisel Usecase: Designing General Matrix Multiply for FPGA. 61-72 - Habib ul Hasan Khan, Ariel Podlubne, Gökhan Akgün, Diana Göhringer:
Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks. 73-83 - Ludovica Bozzoli, Luca Sterpone:
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs. 84-96 - Gökhan Akgün, Habib ul Hasan Khan, Marawan Azmy Hebaish, Mahmoud Ahmed Elshimy, Mohamed A. Abd El Ghany, Diana Göhringer:
SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification. 97-107 - Zakarya Guettatfi, Paul Kaufmann, Marco Platzner:
Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. 108-117
Design Space Exploration and Estimation Techniques
- Pascal Bacchus, Robert J. Stewart, Ekaterina Komendantskaya:
Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs. 121-135 - Leonardo Suriano, David Lima, Eduardo de la Torre:
Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. 136-150 - Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, Smaïl Niar:
Cross-layer CNN Approximations for Hardware Implementation. 151-165 - Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera:
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation. 166-177 - Gökhan Akgün, Lester Kalms, Diana Göhringer:
Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs. 178-192 - Muhammad Ali, Pedram Amini Rad, Diana Göhringer:
RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance. 193-207
High-Level Synthesis
- Hector Gerardo Muñoz Hernandez, Safdar Mahmood, Marcelo Brandalero, Michael Hübner:
A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks. 211-220 - Ashish Misra, Volodymyr V. Kindratenko:
HLS-Based Acceleration Framework for Deep Convolutional Neural Networks. 221-231 - Changdao Du, Iman Firmansyah, Yoshiki Yamaguchi:
FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method. 232-246 - Duc Tri Nguyen, Viet Ba Dang, Kris Gaj:
High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign. 247-257 - Federico Favaro, Ernesto Dufrechou, Pablo Ezzatti, Juan P. Oliver:
Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels. 258-268
Architectures
- George Charitopoulos, Dionisios N. Pnevmatikatos:
A CGRA Definition Framework for Dataflow Applications. 271-287 - Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa:
Implementing CNNs Using a Linear Array of Full Mesh CGRAs. 288-297 - Riadh Ben Abdelhamid, Yoshiki Yamaguchi:
A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment. 298-313 - Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa:
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters. 314-329 - Zhewen Yu, Christos-Savvas Bouganis:
A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny. 330-344 - Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki:
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. 345-357
Applications
- Arshyn Zhanbolatov, Kizheppatt Vipin, Aresh Dadlani, Dmitriy Fedorov:
StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures. 361-375 - M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano:
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System. 376-391 - Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto:
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. 392-401
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