default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDAHS 2018: Edinburgh, UK
- 2018 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2018, Edinburgh, United Kingdom, August 6-9, 2018. IEEE 2018, ISBN 978-1-5386-7753-7
- Adewale Adetomi, Godwin Enemali
, Xabier Iturbe, Tughrul Arslan, Didier Keymeulen:
R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing. 1-8 - Christian M. Fuchs, Nadia M. Murillo, Aske Plaat, Erik van der Kouwe, Todor P. Stefanov:
Dynamic Fault Tolerance Through Resource Pooling. 9-16 - Lev Kirischian, Valeri Kirischian, Dimple Sharma:
Mitigation of Thermo-cycling effects in Flip-chip FPGA-based Space-borne Systems by Cyclic On-chip Task Relocation. 17-24 - Timothee Buettner, Atanas Tanev, Lars Pfotzer, Arne Roennau, Rüdiger Dillmann:
The intelligent Computer Aided Satellite Designer iCASD - Creating viable configurations for modular satellites. 25-32 - Didier Keymeulen, Simon Shin, Jason Riddley, Matthew Klimesh, Aaron B. Kiely, Elliott Liggett, Peter Sullivan, Michael Bernas, Hamid Ghossemi, Greg Flesch, Michael Cheng, Sam Dolinar, David Dolman, Kevin Roth, Chris Holyoake, Ken Crocker, Adam Smith:
High Performance Space Computing with System-on-Chip Instrument Avionics for Space-based Next Generation Imaging Spectrometers (NGIS). 33-36 - Luigi Mascolo, Adrian Stoica:
Electro-Magnetic Launchers on the Moon : A Feasibility Study. 37-42 - Tanya Vladimirova, Muhammad Fayyaz:
Fault-Tolerant Distributed Attitude and Orbit Control System for Space Applications. 43-50 - Arturo Perez, Andrés Otero, Eduardo de la Torre:
Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. 51-58 - Godwin Enemali, Adewale Adetomi, Tughrul Arslan:
Efficient Runtime Frame ECC Recomputation for Reliable Task Execution on Xilinx FPGAs. 59-65 - Alexander Dörflinger, Mark Albers, Johannes Schlatow, Björn Fiethe, Harald Michalik, Phillip Keldenich, Sándor P. Fekete:
Hardware and Software Task Scheduling for ARM-FPGA Platforms. 66-73 - Andrea Guerrieri, Sahand Kashani-Akhavan, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne:
A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. 74-81 - Bilal Nasser, Amir Rabani, Don Freiling, Christian Gan:
An Adaptive Telerobotics Control for Advanced Manufacturing. 82-89 - Víctor Mayoral, Risto Kojcev, Alejandro Hernández, Irati Zamalloa, Asier Bilbao:
Modular And Self-Adaptable (MASA) strategy for building robots. 90-95 - Rachel Dudukovich, Christos Papachristou:
Delay Tolerant Network Routing as a Machine Learning Classification Problem. 96-103 - Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky:
Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. 104-111 - Antonio Sanchez-Clemente, Luis Entrena, Fernanda Lima Kastensmidt:
Approximate TMR for selective error mitigation in FPGAs based on testability analysis. 112-119 - Luca Sterpone, Sarah Azimi, Ludovica Bozzoli, Boyang Du, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Cesar Boatella Polo, David Merodio Codinachs:
A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs. 120-126 - Konstantinos Maragos, Vasileios Leon, George Lentaris, Dimitrios Soudris, David González Arjona, Ruben Domingo, Antonio Pastor, David Merodio Codinachs, Isabelle Conway:
Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA. 127-134 - Klemen Bravhar, Victor Martins, Lucana Santos, David Merodio Codinachs:
BRAVE NG-MEDIUM FPGA reconfiguration through SpaceWire: example use case and performance analysis. 135-141 - Suhaib A. Fahmy:
Design Abstraction for Autonomous Adaptive Hardware Systems on FPGAs. 142-147 - Ismahane Cheheb, Noor Al-Máadeed, Somaya Al-Máadeed, Ahmed Bouridane:
Investigating the Use of Autoencoders for Gait-based Person Recognition. 148-151 - Larbi Boubchir, Yassir Aberni, Boubaker Daachi:
Competitive Coding Scheme based on 2D Log-Gabor filter for Palm Vein Recognition. 152-155 - Imad Rida, Noor Al-Máadeed, Somaya Al-Máadeed:
A Novel Efficient Classwise Sparse and Collaborative Representation for Holistic Palmprint Recognition. 156-161 - Azeddine Beghdadi, Muhammad Asim, Noor Al-Máadeed, Muhammad Ali Qureshi:
Towards the design of smart video-surveillance system. 162-167 - Sima Shariatmadari, Somaya Al-Máadeed, Younes Akbari, Imad Rida, Sima Emadi:
Off-line Persian Signature Verification using Wavelet-based Fractal Dimension and One-class Gaussian Process. 168-173 - Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
Towards a Secure Partial Reconfiguration of Xilinx FPGAs : Special Session Paper. 174-178 - Jonathan Thews, Alan O'Donnell, Alan J. Michaels:
Simulation of 3D Printed Antenna System using Liquid Metal Antenna Elements. 179-183 - Yingmeng Hu, Rongke Liu, Aryan Kaushik, Xiaoyan Shi, John S. Thompson:
A Low Complexity Decoding Algorithm for Spinal Codes with Efficiently Distributed Symbols. 184-191 - Hongxiu Bian, Rongke Liu, Xiaoyan Shi, John S. Thompson:
A High-throughput Fine-grained Rate Adaptive Transmission Scheme for A LEO Satellite Communication System. 192-197 - Zijie Wang, Rongke Liu, Weiqing Mu, Xiaoyan Shi, John S. Thompson:
Adaptive genetic algorithm-based method for antenna location optimization in RF relative measurement. 198-203 - Jayshree, G. Seetharaman:
Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay. 204-209 - Poornima Narayanasamy, Santhi Muthurathinam, Seetharaman Gopalakrishnan, Tughrul Arslan, Sithu D. Sudarsan:
R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip. 210-213 - Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs. 214-217 - Takumi Fujimori, Minoru Watanabe:
A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory. 218-224 - Zhai Zhang, Yao Qiu, Xiaoliang Yuan, Rui Yao, Youren Wang:
Self-healing strategy for transient fault cell reutilization of embryonic array circuit. 225-232 - Rick Wertenbroek, Yann Thoma:
k-mer Counting with FPGAs and HMC In-Memory Operations. 233-240 - Mireya Zapata, Janio Jadán, Jordi Madrenas:
Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus. 241-248 - Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday:
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems. 249-256 - David Grochol, Lukás Sekanina:
Fast Reconfigurable Hash Functions for Network Flow Hashing in FPGAs. 257-263 - Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Design of Quality-Configurable Approximate Multipliers Suitable for Dynamic Environment. 264-271 - Andres Upegui, Bernard Girau, Nicolas P. Rougier, Fabien Vannel, Benoît Miramond:
Pruning Self-Organizing Maps for Cellular Hardware Architectures. 272-279 - Aliyu Dala, Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
RR4DSN: Reconfigurable Receiver for Deepwater Sensor Nodes. 280-284 - Mubariz Zaffar, Shoaib Ehsan, Rustam Stolkin, Klaus D. McDonald-Maier:
Sensors, SLAM and Long-term Autonomy: A Review. 285-290 - Somdip Dey, Grigorios Kalliatakis, Sangeet Saha, Amit Kumar Singh, Shoaib Ehsan, Klaus D. McDonald-Maier:
MAT-CNN-SOPC: Motionless Analysis of Traffic Using Convolutional Neural Networks on System-On-a-Programmable-Chip. 291-298 - Sangeet Saha, Shoaib Ehsan, Adrian Stoica, Rustam Stolkin, Klaus D. McDonald-Maier:
Real-Time Application Processing for FPGA-Based Resilient Embedded Systems in Harsh Environments. 299-304 - Jose Carlos Villarreal Guerra, Zeba Khanam, Shoaib Ehsan, Rustam Stolkin, Klaus D. McDonald-Maier:
Weather Classification: A new multi-class dataset, data augmentation approach and comprehensive evaluations of Convolutional Neural Networks. 305-310 - Alexander J. Martin, Peter J. B. Hancock, Charlie D. Frowd, Priscilla Heard, Emma Gaskin, Claire Ford, Thomas Hewett:
EvoFIT composite face construction via practitioner interviewing and a witness-administered protocol. 311-316 - Saleh Mulhem, Randa Zarrouk, Wael Adi:
Security and Complexity Bounds of SUC-Based Physical Identity. 317-322 - Julian Murphy, Gareth Howells, Klaus D. McDonald-Maier:
On Quaternary 1-of-4 ID Generator Circuits. 323-326 - Emad Hamadaqa, Saleh Mulhem, Ayoub Mars, Wael Adi:
Clone-Resistant Joint-Identity Technique for Securing Fleet Management Systems. 327-332 - Ayoub Mars, Wael Adi:
New Concept for Physically-Secured E-Coins Circulations. 333-338
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-12 20:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
