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"A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction ..."

Won-Joo Yun et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523167

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08
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  persistent URL:
  - https://dblp.org/rec/conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang:
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. ISSCC 2008: 282-283

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