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ORCIDDavid C. Keezer
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- affiliation: Georgia Institute of Technology, Atlanta, USA
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2020 – today
- 2024
[c54]David C. Keezer
, Dany Minier, Hongjie Li:
Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz. ETS 2024: 1-6- [c53]David C. Keezer, Dany Minier:
Multi-Stage Jitter-Reduction and Frequency Multiplication for 54 GHz ATE Clocks. ITC-Asia 2024: 1-6 - 2023
- [c52]David C. Keezer, Dany Minier, Hongjie Li:
Experimental Evaluation of Jitter Reduction Methods for Multi-Gigahertz Test. ITC-Asia 2023: 1-6
2010 – 2019
- 2019
- [j11]Thomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee:
Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition. J. Electron. Test. 35(6): 809-822 (2019) - [c51]Jingchi Yang, David C. Keezer:
A Framework for Design of Self-Repairing Digital Systems. ITC 2019: 1-10 - 2018
- [j10]Taimour Wehbe, Vincent John Mooney III, David C. Keezer:
Hardware-Based Run-Time Code Integrity in Embedded Devices. Cryptogr. 2(3): 20 (2018) - [j9]Taimour Wehbe, Vincent John Mooney, Omer T. Inan, David C. Keezer:
Securing Medical Devices Against Hardware Trojan Attacks Through Analog-, Digital-, and Physiological-Based Signatures. J. Hardw. Syst. Secur. 2(3): 251-265 (2018) - [c50]Taimour Wehbe, Vincent John Mooney, David C. Keezer:
A chip-level security framework for assessing sensor data integrity: work-in-progress. CODES+ISSS 2018: 20 - 2017
- [c49]Taimour Wehbe, Vincent John Mooney, David C. Keezer, Omer T. Inan, Abdul Qadir Javaid:
Use of Analog Signatures for Hardware Trojan Detection. FPGAworld 2017: 15-22 - [c48]David C. Keezer, Jingchi Yang:
Biologically inspired hierarchical structure for self-repairing FPGAs. ReConFig 2017: 1-8 - 2016
- [c47]Te-Hui Chen, David C. Keezer:
An Ultra-High-Speed Test Module and FPGA-Based Development Platform. ATS 2016: 269-274 - [c46]Te-Hui Chen, David C. Keezer:
A 40Gbps economic extension board and FPGA-based testing platform. ETS 2016: 1-2 - 2015
- [c45]Taimour Wehbe, Vincent John Mooney, David C. Keezer, Nicholas B. Parham:
A Novel Approach to Detect Hardware Trojan Attacks on Primary Data Inputs. WESS 2015: 2 - [c44]David C. Keezer, Te-Hui Chen, Thomas Moon, D. T. Stonecypher, Abhijit Chatterjee, Hyun Woo Choi, Sungyeol Kim, Hosun Yoo:
An FPGA-based ATE extension module for low-cost multi-GHz memory test. ETS 2015: 1-6 - 2014
- [c43]Aderinola Gbade-Alabi, David C. Keezer, Vincent John Mooney, Axel York Poschmann, Marc Stöttinger, Kshitij Divekar:
A signature based architecture for Trojan detection. WESS 2014: 3:1-3:10 - [c42]Thomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee:
Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms. VTS 2014: 1-6 - 2013
- [c41]Suvadeep Banerjee, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee:
Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus. Asian Test Symposium 2013: 277-282 - [c40]Satyanarayana Telikepalli, Madhavan Swaminathan, David C. Keezer:
Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling. ISQED 2013: 714-718 - [c39]David C. Keezer, Carl Edward Gray, Te-Hui Chen, Ashraf Majid:
Practical methods for extending ATE to 40 and 50Gbps. ITC 2013: 1-10 - 2012
- [j8]Hsiu-Ming (Sherman) Chang, David C. Keezer:
Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing. J. Electron. Test. 28(5): 555-556 (2012) - [c38]David C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo:
Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. ITC 2012: 1-11 - 2011
- [j7]Carl Edward Gray, David C. Keezer:
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels. J. Electron. Test. 27(3): 351-361 (2011) - [c37]Carl Gray, David C. Keezer, Howard Wang, Keren Bergman:
Burst-Mode Transmission and Data Recovery for Multi-GHz Optical Packet Switching Network Testing. Asian Test Symposium 2011: 545-551 - [c36]David C. Keezer, Carl Edward Gray:
Two methods for 24 Gbps test signal synthesis. DATE 2011: 579-582 - [c35]A. M. Majid, David C. Keezer:
Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. ITC 2011: 1-10 - 2010
- [j6]David C. Keezer, Carl Gray, Dany Minier, Patrice Ducharme:
Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic. J. Electron. Test. 26(1): 87-96 (2010) - [c34]A. M. Majid, David C. Keezer:
Stretching the limits of FPGA SerDes for enhanced ATE performance. DATE 2010: 202-207 - [c33]Marcus Dutton, David C. Keezer:
An architecture for graphics processing in an FPGA (abstract only). FPGA 2010: 283
2000 – 2009
- 2009
- [c32]David C. Keezer, Carl Gray, A. M. Majid, Dany Minier, Patrice Ducharme:
A development platform and electronic modules for automated test up to 20 Gbps. ITC 2009: 1-11 - 2008
- [j5]David C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John McKillop:
MEMS Switches and SiGe Logic for Multi-GHz Loopback Testing. VLSI Design 2008: 291686:1-291686:8 (2008) - [c31]David C. Keezer, Dany Minier, Patrice Ducharme:
Variable Delay of Multi-Gigahertz Digital Signals for Deskew and Jitter-Injection Test Applications. DATE 2008: 1486-1491 - [c30]David C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid:
An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. ITC 2008: 1-9 - 2007
- [c29]David C. Keezer, Dany Minier, Patrice Ducharme:
Method for reducing jitter in multi-gigahertz ATE. DATE 2007: 701-706 - [c28]Carl Edward Gray, Odile Liboiron-Ladouceur, David C. Keezer, Keren Bergman:
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network. ITC 2007: 1-9 - [c27]David C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John McKillop:
Multi-GHz loopback testing using MEMs switches and SiGe logic. ITC 2007: 1-10 - [i1]David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. CoRR abs/0710.4761 (2007) - 2006
- [j4]David C. Keezer, Dany Minier, Patrice Ducharme:
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses. IEEE Des. Test Comput. 23(1): 46-57 (2006) - [c26]A. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru:
Multi-Gigahertz Testing of Wafer-Level Packaged Devices. ITC 2006: 1-10 - 2005
- [c25]A. M. Majid, David C. Keezer, J. V. Karia:
A 5 Gbps Wafer-Level Tester. Asian Test Symposium 2005: 58-63 - [c24]David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. DATE 2005: 152-157 - [c23]David C. Keezer, Carl Gray, Ashraf Majid, Nafeez Taher:
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. ESSCIRC 2005: 291-294 - 2004
- [j3]David C. Keezer, Dany Minier, Marie-Christine Caron:
Multiplexing ATE Channels for Production Testing at 2.5 Gbps. IEEE Des. Test Comput. 21(4): 288-301 (2004) - [c22]David C. Keezer, Dany Minier, F. Binette:
Modular Extension of ATE to 5 Gbps. ITC 2004: 748-757 - 2003
- [c21]John S. Davis, David C. Keezer, Odile Liboiron-Ladouceur, Keren Bergman:
Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober. ITC 2003: 166-174 - [c20]David C. Keezer, Dany Minier, Marie-Christine Caron:
A Production-Oriented Multiplexing System for Testing above 2.5 Gbps. ITC 2003: 191-200 - 2002
- [c19]John S. Davis, David C. Keezer:
Multi-Purpose Digital Test Core Utilizing Programmable Logic. ITC 2002: 438-445 - [c18]David C. Keezer:
Challenges and Solutions for Multi-Gigahertz Testing. ITC 2002: 1230 - [c17]Karim Arabi, Klaus-Dieter Hilliges, David C. Keezer, Sassan Tabatabaei:
Multi-GigaHertz Testing Challenges and Solutions. VTS 2002: 265-268 - 2001
- [c16]David C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole:
Terabit-per-second automated digital testing. ITC 2001: 1143-1151
1990 – 1999
- 1999
- [c15]David C. Keezer, Q. Zhou:
Test support processors for enhanced testability of high performance circuits. ITC 1999: 801-809 - 1998
- [c14]David C. Keezer, K. E. Newman, John S. Davis:
Improved sensitivity for parallel test of substrate interconnections. ITC 1998: 228-233 - [c13]Bruce C. Kim, David C. Keezer, Abhijit Chatterjee:
A high throughput test methodology for MCM substrates. ITC 1998: 234-240 - [c12]David C. Keezer, Q. Zhou:
Alternative interface methods for testing high speed bidirectional signals. ITC 1998: 824-830 - 1997
- [c11]David C. Keezer, R. J. Wenzel:
Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test. ITC 1997: 94-100 - [c10]K. E. Newman, David C. Keezer:
A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates. ITC 1997: 370-378 - 1995
- [c9]David C. Keezer:
Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules. ITC 1995: 917 - 1993
- [c8]N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer:
SMAC: A Scene Matching Chip. ICCD 1993: 184-187 - [c7]David C. Keezer:
Known Godd Die for MCMs: Enabling Technologies. ITC 1993: 266 - 1992
- [j2]Vijay K. Jain, Hiroomi Hikawa, David C. Keezer:
An Architecture for WSI Rapid Prototyping. Computer 25(4): 71-75 (1992) - [c6]David C. Keezer:
MCM Test Using Available Technology. ITC 1992: 253 - [c5]David C. Keezer, R. J. Wenzel:
Calibration Techniques for a Gigahertz Test System. ITC 1992: 530-537 - 1991
- [j1]Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, Denny Whittaker:
Wafer Scale Integration: A university perspective. J. VLSI Signal Process. 2(4): 253-269 (1991) - [c4]David C. Keezer:
Real-Time Data Comparison for GigaHertz Digital Test. ITC 1991: 790-797 - [c3]S. P. Athan, David C. Keezer, J. McKinley:
High Frequency Wafer Probing and Power Supply Resonance Effects. ITC 1991: 1069-1078 - 1990
- [c2]David C. Keezer:
Multiplexing test system channels for data rates above 1 Gb/s. ITC 1990: 362-368
1980 – 1989
- 1985
- [c1]L. J. Falkenstrom, David C. Keezer, A. Patterson, Robert M. Rolfe, J. Wolcott:
Tester Independent Support Software System (TISSS). ITC 1985: 685-691
Coauthor Index
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