default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDaniel Gajski
Daniel D. Gajski
Person information
- affiliation: University of California, Irvine, USA
SPARQL queries 
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2010 – 2019
- 2016
[j52]Fadi J. Kurdahi, Mohammad Abdullah Al Faruque, Daniel Gajski, Ahmed M. Eltawil:
A case study to develop a graduate-level degree program in embedded & cyber-physical systems. SIGBED Rev. 14(1): 16-21 (2016)- 2015
- [j51]Wenliang He, Daniel Gajski, George Farkas, Mark Warschauer:
Implementing flexible hybrid instruction in an electrical engineering course: The best of three worlds? Comput. Educ. 81: 59-68 (2015) - 2014
- [c167]Kyoungwon Kim, Daniel D. Gajski:
Trace-Driven Performance Estimation of multi-core platforms. MWSCAS 2014: 627-630 - [c166]Kyoungwon Kim, Daniel D. Gajski:
Hierarchy-Aware mapping of pipelined applications. MWSCAS 2014: 631-634 - 2012
- [j50]Jelena Trajkovic
, Samar Abdi, Gabriela Nicolescu, Daniel D. Gajski:
Automated Generation of Custom Processor Core from C Code. J. Electr. Comput. Eng. 2012: 862469:1-862469:26 (2012) - 2011
- [j49]Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski:
Automatic TLM Generation for Early Validation of Multicore Systems. IEEE Des. Test Comput. 28(3): 10-19 (2011) - 2010
- [c165]Daniel Gajski, Todd M. Austin, Steve Svoboda:
What input-language is the best choice for high level synthesis (HLS)? DAC 2010: 857-858 - [c164]Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski:
Accurate timed RTOS model for transaction level modeling. DATE 2010: 1333-1336 - [c163]Ines Viskic, Lochi Yu, Daniel Gajski:
Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications. LCTES 2010: 77-84 - [c162]Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski:
Embedded system environment: A framework for TLM-based design and prototyping. International Symposium on Rapid System Prototyping 2010: 1-7 - [c161]Jelena Trajkovic, Daniel D. Gajski:
Early performance-cost estimation of application-specific data path pipelining. SASP 2010: 107-110
2000 – 2009
- 2009
- [j48]Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andrés Takach:
An Introduction to High-Level Synthesis. IEEE Des. Test Comput. 26(4): 8-17 (2009) - [j47]Samar Abdi, Daniel Gajski, Ines Viskic:
Model Based Synthesis of Embedded Software. J. Softw. 4(7): 717-727 (2009) - [j46]Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich:
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1517-1530 (2009) - [c160]Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski:
Hardware-dependent software synthesis for many-core embedded systems. ASP-DAC 2009: 304-310 - 2008
- [j45]Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski:
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008) - [j44]Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs. ACM Trans. Reconfigurable Technol. Syst. 1(2): 11:1-11:21 (2008) - [j43]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 466-475 (2008) - [c159]Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP). DAC 2008: 72-75 - [c158]Bita Gorjiara, Daniel Gajski:
Automatic architecture refinement techniques for customizing processing elements. DAC 2008: 379-384 - [c157]Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara:
Specify-explore-refine (SER): from specification to implementation. DAC 2008: 586-591 - [c156]Yonghyun Hwang, Samar Abdi, Daniel Gajski:
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. DATE 2008: 3-8 - [c155]Jelena Trajkovic, Daniel D. Gajski:
Custom Processor Core Construction from C Code. SASP 2008: 1-6 - [c154]Daniel D. Gajski, Samar Abdi, Ines Viskic:
Model Based Synthesis of Embedded Software. SEUS 2008: 21-33 - 2007
- [j42]Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1676-1687 (2007) - [c153]Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil:
TLM: Crossing Over From Buzz To Adoption. DAC 2007: 444-445 - [c152]Mehrdad Reshadi, Daniel Gajski:
Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems. DATE 2007: 1337-1342 - [c151]Daniel D. Gajski:
New Strategies for System-Level Design. DDECS 2007: 15 - [c150]Bita Gorjiara, Daniel Gajski:
FPGA-friendly code compression for horizontal microcoded custom IPs. FPGA 2007: 108-115 - [c149]Bita Gorjiara, Daniel Gajski:
A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs. ICCD 2007: 609-614 - [c148]Jelena Trajkovic, Daniel Gajski:
Automatic Data Path Generation from C code for Custom Processors. IESS 2007: 107-120 - [c147]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144 - [c146]Hansu Cho, Samar Abdi, Daniel Gajski:
Interface synthesis for heterogeneous multi-core systems from transaction level models. LCTES 2007: 140-142 - [c145]Ines Viskic, Samar Abdi, Daniel D. Gajski:
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. LCTES 2007: 143-145 - 2006
- [j41]Samar Abdi, Daniel Gajski:
Verification of System Level Model Transformations. Int. J. Parallel Program. 34(1): 29-59 (2006) - [c144]Bita Gorjiara, Mehrdad Reshadi, Daniel D. Gajski:
Designing a custom architecture for DCT using NISC technology. ASP-DAC 2006: 116-117 - [c143]Hansu Cho, Samar Abdi, Daniel Gajski:
Design and implementation of transducer for ARM-TMS communication. ASP-DAC 2006: 126-127 - [c142]Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69 - [c141]Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski:
Generic netlist representation for system and PE level design exploration. CODES+ISSS 2006: 282-287 - [c140]Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski:
A Graph Based Algorithm for Data Path Optimization in Custom Processors. DSD 2006: 496-503 - [c139]Samar Abdi, Daniel Gajski:
Transaction Routing and its Verification by Correct Model Transformations. HLDVT 2006: 129-136 - [c138]Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . ICCD 2006: 356-361 - 2005
- [c137]Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48 - [c136]Samar Abdi, Daniel Gajski:
A formalism for functionality preserving system level transformations. ASP-DAC 2005: 139-144 - [c135]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Multi-metric and multi-entity characterization of applications for early system design exploration. ASP-DAC 2005: 944-947 - [c134]Junyu Peng, Samar Abdi, Daniel Gajski:
A clustering technique to optimize hardware/software synchronization. ASP-DAC 2005: 965-968 - [c133]Mehrdad Reshadi, Daniel Gajski:
A cycle-accurate compilation algorithm for custom pipelined datapaths. CODES+ISSS 2005: 21-26 - [c132]Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser:
What will system level design be when it grows up? CODES+ISSS 2005: 123 - [c131]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260 - [c130]Samar Abdi, Daniel D. Gajski:
Functional Validation of System Level Static Scheduling. DATE 2005: 542-547 - [c129]Shuqing Zhao, Daniel D. Gajski:
Defining an Enhanced RTL Semantics. DATE 2005: 548-553 - [c128]Bita Gorjiara, Daniel D. Gajski:
Custom Processor Design Using NISC: A Case-Study on DCT algorithm. ESTIMedia 2005: 55-60 - [c127]Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski:
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ICCD 2005: 69-76 - [c126]Haobo Yu, Rainer Dömer, Daniel D. Gajski:
Software and Driver Synthesis from Transaction Level Models. IESS 2005: 65-76 - [c125]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic Generation of Communication Architectures. IESS 2005: 179-188 - [c124]Shuqing Zhao, Daniel D. Gajski:
Structural operational semantics for supporting multi-cycle operations in RTL HDLs. MEMOCODE 2005: 45-53 - [c123]Daniel Gajski:
System design extreme makeover. MEMOCODE 2005: 71-75 - 2004
- [c122]Samar Abdi, Daniel Gajski:
On deriving equivalent architecture model from system specification. ASP-DAC 2004: 322-327 - [c121]Haobo Yu, Rainer Dömer, Daniel Gajski:
Embedded software generation from system level design languages. ASP-DAC 2004: 463-468 - [c120]Dongwan Shin, Samar Abdi, Daniel Gajski:
Automatic generation of bus functional models from transaction level models. ASP-DAC 2004: 756-758 - [c119]Lukai Cai, Haobo Yu, Daniel Gajski:
A novel memory size model for variable-mapping in system level design. ASP-DAC 2004: 812-817 - [c118]Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist:
Embedded systems education: how to teach the required skills? CODES+ISSS 2004: 254-255 - [c117]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Retargetable profiling for rapid, early system-level design space exploration. DAC 2004: 281-286 - [c116]Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon:
Were the good old days all that good?: EDA then and now. DAC 2004: 543 - [c115]Samar Abdi, Daniel Gajski:
Automatic generation of equivalent architecture model from functional specification. DAC 2004: 608-613 - [c114]Samar Abdi, Daniel Gajski:
Model validation for mapping specification behaviors to processing elements. HLDVT 2004: 101-106 - 2003
- [c113]Lukai Cai, Daniel Gajski:
Transaction level modeling: an overview. CODES+ISSS 2003: 19-24 - [c112]Haobo Yu, Andreas Gerstlauer, Daniel Gajski:
RTOS scheduling in transaction level models. CODES+ISSS 2003: 31-36 - [c111]Samar Abdi, Dongwan Shin, Daniel Gajski:
Automatic communication refinement for system level design. DAC 2003: 300-305 - [c110]Andreas Gerstlauer, Haobo Yu, Daniel Gajski:
RTOS Modeling for System Level Design. DATE 2003: 10130-10135 - [c109]Heinz-Josef Schlebusch, Gary Smith, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel:
Transaction Based Design: Another Buzzword or the Solution to a Design Problem? DATE 2003: 10876-10879 - [p1]Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski:
RTOS Modeling for System Level Design. Embedded Software for SoC 2003: 55-68 - 2002
- [j40]Jianwen Zhu, Daniel D. Gajski:
An ultra-fast instruction set simulator. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 363-373 (2002) - [c108]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Co-design of embedded controllers for power electronics and electric systems. ISIC 2002: 379-383 - [c107]Lukai Cai, Daniel Gajski, Paul Kritzinger, Mike Olivarez:
Top-Down System Level Design Methodology Using SpecC, VCC and SystemC. DATE 2002: 1137 - [c106]Shuqing Zhao, Daniel Gajski:
Modeling a new RTL semantics in C++. ISCAS (5) 2002: 741-744 - [c105]Daniel Gajski, Junyu Peng:
Optimal Message-Passing for Data Coherency in Distributed Architecture. ISSS 2002: 20-25 - [c104]Daniel Gajski, Andreas Gerstlauer:
System-Level Abstraction Semantics. ISSS 2002: 231-236 - [c103]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Seamless approach for the design of control systems for power electronics and electric drives. SMC 2002: 6 - [c102]Junyu Peng, Samar Abdi, Daniel Gajski:
Automatic Model Refinement for Fast Architecture Exploration. ASP-DAC/VLSI Design 2002: 332-337 - 2001
- [b2]Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski:
System Design - A Practical Guide with SpecC. Springer 2001, ISBN 978-0-7923-7387-2, pp. 1-255 - [j39]Smita Bakshi, Daniel Gajski:
Performance-constrained hierarchical pipelining for behaviors, loops, and operations. ACM Trans. Design Autom. Electr. Syst. 6(1): 1-25 (2001) - [c101]Jianwen Zhu, Daniel Gajski:
Compiling SpecC for simulation. ASP-DAC 2001: 57-62 - [c100]Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont:
Panel: The Next HDL: If C++ is the Answer, What was the Question? DAC 2001: 71-72 - [c99]Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong:
C/C++: progress or deadlock in system-level specification. DATE 2001: 136-137 - [c98]Lukai Cai, Daniel Gajski, Mike Olivarez:
Introduction of system level architecture exploration using the SpecC methodology. ISCAS (5) 2001: 9-12 - [c97]Brian Bailey, Daniel Gajski:
RTL semantics and methodology. ISSS 2001: 69-74 - 2000
- [c96]Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud:
Embedded tutorial: essential issues for IP reuse. ASP-DAC 2000: 37-42 - [c95]Nong Fan, Viraphol Chaiyakul, Daniel Gajski:
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. ASP-DAC 2000: 43-48 - [c94]Rainer Dömer, Daniel Gajski:
Reuse and protection of intellectual property in the SpecC system. ASP-DAC 2000: 49-54 - [c93]Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura:
One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654 - [c92]Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann:
The Specification Language SpecC within the PARADISE Design Environment. DIPES 2000: 111-120
1990 – 1999
- 1999
- [j38]Smita Bakshi, Daniel D. Gajski:
Partitioning and pipelining for performance-constrained hardware/software systems. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 419-432 (1999) - [c91]Jianwen Zhu, Daniel Gajski:
A unified formal model of ISA and FSMD. CODES 1999: 121-125 - [c90]Daniel Gajski:
IP-based Design Methodology. DAC 1999: 43 - [c89]Jianwen Zhu, Daniel Gajski:
Soft Scheduling in High Level Synthesis. DAC 1999: 219-224 - [c88]Jianwen Zhu, Daniel Gajski:
OpenJ: An Extensible System Level Design Language. DATE 1999: 480-484 - [c87]Dai Araki, Tadatoshi Ishii, Daniel Gajski:
Rapid Prototyping with HW/SW Codesign Tool. ECBS 1999: 114-121 - [c86]Daniel Gajski, Reinaldo A. Bergamaschi:
Panel Statement: System-Level Design: Designers' Wish List vs. Reality. ISSS 1999: 8-9 - 1998
- [j37]Rainer Dömer, Daniel D. Gajski, Jianwen Zhu:
Specification and Design of Embedded Systems. Informationstechnik Tech. Inform. 40(3): 7-12 (1998) - [j36]Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 84-100 (1998) - [c85]Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
System-level exploration with SpecSyn. DAC 1998: 812-817 - [c84]Smita Bakshi, Daniel D. Gajski:
Hierarchical pipelining for behaviors, loops, and operations. ICCD 1998: 450-455 - [c83]Daniel Gajski, Rainer Dömer, Jianwen Zhu:
IP-Centric Methodology and Specification Language. DIPES 1998: 3-22 - 1997
- [j35]Jie Gong, Daniel Gajski, Smita Bakshi:
Model refinement for hardware-software codesign. ACM Trans. Design Autom. Electr. Syst. 2(1): 22-41 (1997) - [c82]Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski:
A quantitative analysis for optimizing memory allocation. ASP-DAC 1997: 239-245 - [c81]Smita Bakshi, Daniel Gajski:
Hardware/Software Partitioning and Pipelining. DAC 1997: 713-716 - [c80]Smita Bakshi, Daniel Gajski:
A Scheduling and Pipelining Algorithm for Hardware/Software Systems. ISSS 1997: 113- - 1996
- [j34]En-Shou Chang, Daniel Gajski, Sanjiv Narayan:
An optimal clock period selection method based on slack minimization criteria. ACM Trans. Design Autom. Electr. Syst. 1(3): 352-370 (1996) - [j33]Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung:
System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 70-82 (1996) - [j32]Smita Bakshi, Daniel D. Gajski:
Component selection for high-performance pipelines. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 181-194 (1996) - [c79]Jie Gong, Daniel D. Gajski, Smita Bakshi:
Model Refinement for Hardware-Software Codesign. ED&TC 1996: 270-274 - [c78]Sanjiv Narayan, Daniel D. Gajski:
Rapid performance estimation for system design. EURO-DAC 1996: 206-211 - [c77]Hsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski:
Clock optimization for high-performance pipelined design. EURO-DAC 1996: 330-335 - [c76]Smita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan:
Component selection in resource shared and pipelined DSP applications. EURO-DAC 1996: 370-375 - [c75]Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul:
Clock-driven performance optimization in interactive behavioral synthesis. ICCAD 1996: 154-157 - [c74]Rajesh K. Gupta, Daniel Gajski, Randy Allen, Yatin Trivedi:
Opportunities and pitfalls in HDL-based system design. ICCD 1996: 56-57 - 1995
- [j31]Daniel D. Gajski, Frank Vahid:
Specification and Design of Embedded Hardware-Software Systems. IEEE Des. Test Comput. 12(1): 53-67 (1995) - [j30]Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 694-706 (1995) - [j29]Frank Vahid, Daniel D. Gajski:
Incremental hardware estimation during hardware/software functional partitioning. IEEE Trans. Very Large Scale Integr. Syst. 3(3): 459-464 (1995) - [j28]Jie Gong, Daniel D. Gajski, Alexandru Nicolau:
Performance evaluation for application-specific architectures. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 483-490 (1995) - [c73]Sanjiv Narayan, Daniel Gajski:
Interfacing Incompatible Protocols Using Interface Process Generation. DAC 1995: 468-473 - [c72]Frank Vahid, Daniel D. Gajski:
SLIF: a specification-level intermediate format for system design. ED&TC 1995: 185-189 - [c71]Nancy D. Holmes, Daniel D. Gajski:
Architectural exploration for datapaths with memory hierarchy. ED&TC 1995: 340-344 - [c70]Jie Gong, Daniel D. Gajski, Sanjiv Narayan:
Software estimation using a generic-processor model. ED&TC 1995: 498-502 - [c69]Smita Bakshi, Daniel D. Gajski:
A memory selection algorithm for high-performance pipelines. EURO-DAC 1995: 124-129 - [c68]Frank Vahid, Daniel D. Gajski:
Closeness metrics for system-level functional partitioning. EURO-DAC 1995: 328-333 - [c67]Frank Vahid, Daniel D. Gajski:
Clustering for improved system-level functional partitioning. ISSS 1995: 28-35 - 1994
- [j27]Daniel D. Gajski, Loganath Ramachandran:
Introduction to High-Level Synthesis. IEEE Des. Test Comput. 11(4): 44-54 (1994) - [j26]Tsing-Fa Lee, Allen C.-H. Wu, Youn-Long Lin, Daniel D. Gajski:
A transformation-based method for loop folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 439-450 (1994) - [c66]Sanjiv Narayan, Daniel Gajski:
Protocol Generation for Communication Channels. DAC 1994: 547-551 - [c65]Jie Gong, Daniel D. Gajski, Alex Nicolau:
A performance evaluator for parameterized ASIC architectures. EURO-DAC 1994: 66-71 - [c64]Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung:
100-hour design cycle: a test case. EURO-DAC 1994: 144-149 - [c63]Frank Vahid, Daniel D. Gajski, Jie Gong:
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning. EURO-DAC 1994: 214-219 - [c62]Loganath Ramachandran, Daniel Gajski, Viraphol Chaiyakul:
An Algorithm for Array Variable Clustering. EDAC-ETC-EUROASIC 1994: 262-266 - [c61]Nancy D. Holmes, Daniel Gajski:
An Algorithm for Generation of Behavioral Shape Functions. EDAC-ETC-EUROASIC 1994: 314-318 - [c60]Sanjiv Narayan, Daniel Gajski:
Synthesis of System-Level Bus Interfaces. EDAC-ETC-EUROASIC 1994: 395-399 - [c59]Smita Bakshi, Daniel D. Gajski:
A component selection algorithm for high-performance pipelines. EURO-DAC 1994: 400-405 - [c58]Daniel Gajski, Frank Vahid, Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement. EDAC-ETC-EUROASIC 1994: 458-463 - [c57]Frank Vahid, Daniel D. Gajski, Sanjiv Narayan:
A transformation for integrating VHDL behavioral specification with synthesis and software generation. EURO-DAC 1994: 552-557 - [c56]Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski:
Condition graphs for high-quality behavioral synthesis. ICCAD 1994: 170-174 - [c55]Smita Bakshi, Daniel D. Gajski:
Design exploration for high-performance pipelines. ICCAD 1994: 312-316 - 1993
- [j25]Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic:
Component synthesis from functional descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1287-1299 (1993) - [c54]Viraphol Chaiyakul, Daniel Gajski, Loganath Ramachandran:
High-Level Transformations for Minimizing Syntactic Variances. DAC 1993: 413-418 - [c53]Loganath Ramachandran, Daniel D. Gajski:
Architectural tradeoffs in synthesis of pipelined controls. EURO-DAC 1993: 244-249 - [c52]Hsiao-Ping Juan, Nancy D. Holmes, Smita Bakshi, Daniel D. Gajski:
Top-down modeling of RISC processors in VHDL. EURO-DAC 1993: 454-459 - [c51]Sanjiv Narayan, Daniel D. Gajski:
Features supporting system-level specification in HDLs. EURO-DAC 1993: 540-545 - [c50]Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Synthesis of functions and procedures in behavioral VHDL. EURO-DAC 1993: 560-565 - 1992
- [b1]Daniel D. Gajski, Nikil D. Dutt, Allen C.-H. Wu:
Youn-Long Steve Lin. Springer 1992, ISBN 978-1-4613-6617-1, pp. 1-359 - [j24]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Specification with the SpecCharts Language. IEEE Des. Test Comput. 9(4): 6-13 (1992) - [j23]Lawrence L. Larmore, Daniel D. Gajski, Allen C.-H. Wu:
Layout placement for sliced architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1): 102-114 (1992) - [j22]Allen C.-H. Wu, Daniel D. Gajski:
Partitioning algorithms for layout synthesis from register-transfer netlists. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 453-463 (1992) - [c49]Frank Vahid, Daniel Gajski:
Specification Partitioning for System Design. DAC 1992: 219-224 - [c48]Elke A. Rundensteiner, Daniel Gajski:
Functional Synthesis Using Area and Delay Optimization. DAC 1992: 291-296 - [c47]Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski:
Timing models for high-level synthesis. EURO-DAC 1992: 60-65 - [c46]Sanjiv Narayan, Daniel D. Gajski:
System clock estimation based on clock slack minimization. EURO-DAC 1992: 66-71 - [c45]Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
Semantics and synthesis of signals in behavioral VHDL. EURO-DAC 1992: 616-621 - [c44]Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin:
An effective methodology for functional pipelining. ICCAD 1992: 230-233 - [c43]Allen C.-H. Wu, Tedd Hadley, Daniel Gajski:
An efficient multi-view design model for real-time interactive synthesis. ICCAD 1992: 328-331 - [c42]Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul:
Accurate layout area and delay modeling for system level design. ICCAD 1992: 355-361 - [c41]Daniel Gajski, Nikil D. Dutt:
Benchmarking and the Art of Syntesis Tool Comparison. Synthesis for Control Dominated Circuits 1992: 439-453 - [c40]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Level Specification and Synthesis. VLSI Design 1992: 103-108 - 1991
- [c39]Allen C.-H. Wu, Daniel D. Gajski:
Glue-logic partitioning for floorplans with a rectilinear datapath. EURO-DAC 1991: 162-166 - [c38]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Translating system specifications to VHDL. EURO-DAC 1991: 390-394 - [c37]Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski:
Layout-Area Models for High-Level Synthesis. ICCAD 1991: 34-37 - [c36]Loganath Ramachandran, Daniel Gajski:
An Algorithm for Component Selection in Performance Optimized Scheduling. ICCAD 1991: 92-95 - [c35]Sanjiv Narayan, Frank Vahid, Daniel Gajski:
System Specification and Synthesis with the SpecCharts Language. ICCAD 1991: 266-269 - [c34]Frank Vahid, Daniel Gajski:
Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation. ICCAD 1991: 362-365 - 1990
- [j21]Nikil D. Dutt, Daniel D. Gajski:
Design Synthesis and Silicon Compilation. IEEE Des. Test Comput. 7(6): 8-23 (1990) - [j20]James R. Kipps, Daniel D. Gajski:
The Role of Learning in Logic Synthesis. Int. J. Pattern Recognit. Artif. Intell. 4(2): 167-180 (1990) - [j19]Forrest Brewer, Daniel D. Gajski:
Chippe: a system for constraint driven behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 681-695 (1990) - [j18]Min-You Wu, Daniel Gajski:
Hypertool: A Programming Aid for Message-Passing Systems. IEEE Trans. Parallel Distributed Syst. 1(3): 330-343 (1990) - [c33]Nikil D. Dutt, Tedd Hadley, Daniel Gajski:
An Intermediate Representation for Behavioral Synthesis. DAC 1990: 14-19 - [c32]Gwo-Dong Chen, Daniel Gajski:
An Intelligent Component Database for Behavioral Synthesis. DAC 1990: 150-155 - [c31]Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski:
Percolation Based Synthesis. DAC 1990: 444-449 - [c30]Mehrdad Negahban, Daniel Gajski:
Silicon compilation of switched: capacitor networks. EURO-DAC 1990: 164-168 - [c29]Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski:
A new algorithm for transistor sizing in CMOS circuits. EURO-DAC 1990: 589-593 - [c28]Allen C.-H. Wu, Daniel Gajski:
Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. ICCAD 1990: 144-147 - [c27]Elke A. Rundensteiner, Daniel Gajski, Lubomir Bic:
The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. ICCAD 1990: 208-211
1980 – 1989
- 1989
- [j17]Chidchanok Lursinsap, Daniel Gajski:
Power routing in channelless floorplan layouts. Integr. 8(3): 249-268 (1989) - [j16]Min-You Wu, Daniel D. Gajski:
Computer-aided programming for message-passing systems: problems and solutions. Proc. IEEE 77(12): 1983-1991 (1989) - [c26]Joseph Lis, Daniel Gajski:
VHDL Synthesis Using Structured Modeling. DAC 1989: 606-609 - [c25]Nikil D. Dutt, Daniel Gajski:
Designer Controlled Behavioral Synthesis. DAC 1989: 754-757 - [c24]Min-You Wu, Daniel Gajski:
Hypertool: A Programming Aid for Multicomputers. ICPP (2) 1989: 15-18 - [c23]James R. Kipps, Daniel D. Gajski:
The role of learning in logic synthesis. TAI 1989: 252-258 - 1988
- [j15]Youn-Long Lin, Daniel D. Gajski:
LES: a layout expert system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 868-876 (1988) - [j14]Chidchanok Lursinsap, Daniel D. Gajski:
A technique for pull-up transistor folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 887-896 (1988) - [j13]Min-You Wu, Daniel D. Gajski:
A programming aid for hypercube architectures. J. Supercomput. 2(3): 349-372 (1988) - [c22]Nels Vander Zanden, Daniel Gajski:
MILO: A Microarchitecture and Logic Optimizer. DAC 1988: 403-408 - [c21]Joseph Lis, Daniel D. Gajski:
Synthesis from VHDL. ICCD 1988: 378-381 - 1987
- [j12]Barry M. Pangrle, Daniel D. Gajski:
Design Tools for Intelligent Silicon Compilation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1098-1112 (1987) - [c20]Forrest Brewer, Daniel Gajski:
Knowledge Based Control in Micro-Architecture Design. DAC 1987: 203-209 - [c19]Chidchanok Lursinsap, Daniel Gajski:
Improving a PLA Area by Pull-Up Transistor Folding. DAC 1987: 608-614 - [c18]Youn-Long Lin, Daniel Gajski:
LES: A Layout Expert System. DAC 1987: 672-678 - [c17]Min-You Wu, Daniel Gajski:
A Programming Aid for Message-passing Systems. PP 1987: 328-332 - 1986
- [j11]Avinoam Bilgory, Daniel Gajski:
A Heuristic for Suffix Solutions. IEEE Trans. Computers 35(1): 34-42 (1986) - [c16]Forrest Brewer, Daniel Gajski:
An expert-system paradigm for design. DAC 1986: 62-68 - [c15]Alex Orailoglu, Daniel Gajski:
Flow graph representation. DAC 1986: 503-509 - [c14]Jih-Kwon Peir, Daniel Gajski:
CAMP: A Programming Aide for Multiprocessors. ICPP 1986: 475-482 - 1985
- [j10]Daniel Gajski, Jih-Kwon Peir:
Essential Issues in Multiprocessor Systems. Computer 18(6): 9-27 (1985) - [j9]Daniel Gajski, Jih-Kwon Peir:
Comparison of five multiprocessor systems. Parallel Comput. 2(3): 265-282 (1985) - [c13]Steven T. Healey, Daniel D. Gajski:
Decomposition of logic networks into silicon. DAC 1985: 162-168 - [e1]Daniel D. Gajski, Ahmed H. Sameh, Kai Hwang:
7th IEEE Symposium on Computer Arithmetic, ARITH 1985, Urbana, IL, USA, June 4-6, 1985. IEEE 1985, ISBN 0-8186-0632-0 [contents] - 1984
- [j8]Utpal Banerjee, Daniel Gajski:
Fast Execution of Loops with IF Statements. IEEE Trans. Computers 33(11): 1030-1033 (1984) - [j7]Won Kim, Daniel Gajski, David J. Kuck:
A Parallel Pipelined Relational Query Processor. ACM Trans. Database Syst. 9(2): 214-242 (1984) - [c12]Daniel D. Gajski, Duncan H. Lawrie, David J. Kuck, Ahmed H. Sameh:
Cedar. COMPCON 1984: 306-310 - [c11]Daniel D. Gajski:
Silicon compilers and expert systems for VLSI. DAC 1984: 86-87 - [c10]Chidchanok Lursinsap, Daniel Gajski:
Cell compilation with constraints. DAC 1984: 103-108 - [c9]Vijay K. Raj, Barry M. Pangrle, Daniel D. Gajski:
Microprocessor synthesis. DAC 1984: 676-678 - [c8]Utpal Banerjee, Daniel Gajski:
Fast Execution of Loops With IF Statements. ISCA 1984: 126-132 - [c7]Daniel Gajski, Won Kim, Shinya Fushimi:
A Parallel Pipelined Relational Query Processor: An Architectural Overview. ISCA 1984: 134-141 - 1983
- [j6]Daniel Gajski, Robert H. Kuhn:
New VLSI Tools - Guest Editors' Introduction. Computer 16(12): 11-14 (1983) - [j5]Daniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh:
CEDAR: a large scale multiprocessor. SIGARCH Comput. Archit. News 11(1): 7-11 (1983) - [c6]Daniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh:
Cedar : A Large Scale Multiprocessor. ICPP 1983: 524-529 - 1982
- [j4]Daniel Gajski, David A. Padua, David J. Kuck, Robert H. Kuhn:
A Second Opinion on Data Flow Machines and Languages. Computer 15(2): 58-69 (1982) - [c5]Daniel D. Gajski, Ahmed H. Sameh, John A. Wisniewski:
Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor. ICPP 1982: 82-89 - 1981
- [j3]Daniel Gajski:
An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines. IEEE Trans. Computers 30(3): 190-206 (1981) - [j2]Jacob A. Abraham, Daniel Gajski:
Design of Testable Structures Defined by Simple Loops. IEEE Trans. Computers 30(11): 875-884 (1981) - [c4]Daniel Gajski:
Recurrence semigroups and their relation to data storage in fast recurrence solvers on parallel machines. CONPAR 1981: 343-357 - [c3]Avinoam Bilgory, Daniel D. Gajski:
Automatic generation of cells for recurrence structures. DAC 1981: 306-313 - 1980
- [j1]Daniel Gajski:
Parallel Compressors. IEEE Trans. Computers 29(5): 393-398 (1980) - [c2]Albert E. Casavant, Daniel D. Gajski, David J. Kuck:
Automatic design with dependence graphs. DAC 1980: 506-515
1970 – 1979
- 1978
- [c1]Daniel D. Gajski, Louis P. Rubinfield:
Design of arithmetic elements for Burroughs Scientific Processor. IEEE Symposium on Computer Arithmetic 1978: 245-256
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-07-04 21:30 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
