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2020 – today
- 2024
[c36]Wim Heirman, Stijn Eyerman:
Message from the Program Chairs; ISPASS 2024. ISPASS 2024: xii-xiii- [i3]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Accurate and Scalable Many-Node Simulation. CoRR abs/2401.09877 (2024) - 2023
- [j28]Sriram Aananthakrishnan
, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche:
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43(5): 78-87 (2023) - [c35]Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur:
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS 2023: 124-133 - 2022
- [j27]Dimitri Kagaris, Sourav Dutta, Stijn Eyerman:
Execution Time Estimation of Multithreaded Programs With Critical Sections. IEEE Trans. Parallel Distributed Syst. 33(10): 2470-2481 (2022) - [c34]Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout:
Scale-Model Architectural Simulation. ISPASS 2022: 58-68 - [c33]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS 2022: 322-331 - [i2]Stijn Eyerman, Ibrahim Hur:
Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. CoRR abs/2209.13265 (2022) - 2021
- [j26]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. 20(1): 78-81 (2021) - [j25]Stijn Eyerman, Wim Heirman, Ibrahim Hur:
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. 20(2): 90-93 (2021) - [j24]Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout:
Scale-Model Simulation. IEEE Comput. Archit. Lett. 20(2): 175-178 (2021) - [j23]Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur:
Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. 18(3): 33:1-33:23 (2021) - [c32]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO 2021: 767-778 - 2020
- [j22]Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur:
Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. 19(1): 30-33 (2020) - [c31]Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur:
Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC 2020: 1-7 - [i1]Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz:
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR abs/2010.06277 (2020)
2010 – 2019
- 2018
- [j21]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. 17(1): 55-58 (2018) - [j20]Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout:
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors. IEEE Trans. Computers 67(6): 830-846 (2018) - [c30]Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur:
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT 2018: 28:1-28:11 - [c29]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur:
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS 2018: 179-188 - [c28]Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur:
Many-core graph workload analysis. SC 2018: 22:1-22:11 - 2017
- [j19]Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. 16(1): 56-59 (2017) - [j18]Sander De Pestel, Stijn Eyerman, Lieven Eeckhout:
Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way. IEEE Trans. Computers 66(3): 458-472 (2017) - [j17]Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit, Lieven Eeckhout:
Improving IBM POWER8 Performance Through Symbiotic Job Scheduling. IEEE Trans. Parallel Distributed Syst. 28(10): 2838-2851 (2017) - [c27]Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout:
Reliability-Aware Scheduling on Heterogeneous Multicore Processors. HPCA 2017: 397-408 - [c26]Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis:
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. HPEC 2017: 1-7 - [c25]Jennifer B. Sartor, Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout:
Analyzing the scalability of managed language applications with speedup stacks. ISPASS 2017: 23-32 - 2016
- [j16]Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Maximizing Heterogeneous Processor Performance Under Power Constraints. ACM Trans. Archit. Code Optim. 13(3): 29:1-29:23 (2016) - [j15]Sam Van den Steen, Stijn Eyerman, Sander De Pestel, Moncef Mechri, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout:
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Computers 65(12): 3537-3551 (2016) - [c24]Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit:
Symbiotic job scheduling on the IBM POWER8. HPCA 2016: 669-680 - 2015
- [j14]Arun Arvind Nair, Stijn Eyerman, Jian Chen, Lizy Kurian John, Lieven Eeckhout:
Mechanistic Modeling of Architectural Vulnerability Factor. ACM Trans. Comput. Syst. 32(4): 11:1-11:32 (2015) - [c23]Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout:
Micro-architecture independent analytical processor performance and power modeling. ISPASS 2015: 32-41 - [c22]Stijn Eyerman, Pierre Michaud, Wouter Rogiest:
Revisiting symbiotic job scheduling. ISPASS 2015: 124-134 - [c21]Sander De Pestel, Stijn Eyerman, Lieven Eeckhout:
Micro-architecture independent branch behavior characterization. ISPASS 2015: 135-144 - 2014
- [j13]Stijn Eyerman, Lieven Eeckhout:
Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance. IEEE Comput. Archit. Lett. 13(2): 93-96 (2014) - [j12]Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout:
An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. 11(3): 28:1-28:25 (2014) - [j11]Stijn Eyerman, Pierre Michaud, Wouter Rogiest:
Multiprogram Throughput Metrics: A Systematic Approach. ACM Trans. Archit. Code Optim. 11(3): 34:1-34:26 (2014) - [j10]Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout:
Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance. ACM Trans. Archit. Code Optim. 11(4): 50:1-50:26 (2014) - [c20]Stijn Eyerman, Lieven Eeckhout:
The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. ASPLOS 2014: 591-606 - 2013
- [j9]Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout:
Per-thread cycle accounting in multicore processors. ACM Trans. Archit. Code Optim. 9(4): 29:1-29:22 (2013) - [c19]Kristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout:
Criticality stacks: identifying critical threads in parallel programs using synchronization behavior. ISCA 2013: 511-522 - [c18]Kristof Du Bois, Jennifer B. Sartor, Stijn Eyerman, Lieven Eeckhout:
Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications. OOPSLA 2013: 355-372 - 2012
- [j8]Stijn Eyerman, Lieven Eeckhout:
Probabilistic modeling for job symbiosis scheduling on SMT processors. ACM Trans. Archit. Code Optim. 9(2): 7:1-7:27 (2012) - [c17]Osman Allam, Stijn Eyerman, Lieven Eeckhout:
An efficient CPI stack counter architecture for superscalar processors. ACM Great Lakes Symposium on VLSI 2012: 55-58 - [c16]Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John:
A first-order mechanistic model for architectural vulnerability factor. ISCA 2012: 273-284 - [c15]Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout:
A mechanistic performance model for superscalar in-order processors. ISPASS 2012: 14-24 - [c14]Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout:
Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. ISPASS 2012: 145-155 - 2011
- [j7]Stijn Eyerman, Lieven Eeckhout:
Fine-grained DVFS using on-chip regulators. ACM Trans. Archit. Code Optim. 8(1): 1:1-1:24 (2011) - [c13]Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout:
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. ISPASS 2011: 216-226 - [c12]Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout:
How sensitive is processor customization to the workload's input datasets? SASP 2011: 1-7 - 2010
- [j6]Stijn Eyerman, Lieven Eeckhout:
Per-Thread Cycle Accounting. IEEE Micro 30(1): 71-80 (2010) - [j5]Stijn Eyerman, Lieven Eeckhout:
A Counter Architecture for Online DVFS Profitability Estimation. IEEE Trans. Computers 59(11): 1576-1583 (2010) - [c11]Stijn Eyerman, Lieven Eeckhout:
Probabilistic job symbiosis modeling for SMT processor scheduling. ASPLOS 2010: 91-102 - [c10]Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout:
Interval simulation: Raising the level of abstraction in architectural simulation. HPCA 2010: 1-12 - [c9]Stijn Eyerman, Lieven Eeckhout:
Modeling critical sections in Amdahl's law and its implications for multicore design. ISCA 2010: 362-370
2000 – 2009
- 2009
- [j4]Stijn Eyerman, Lieven Eeckhout:
Memory-level parallelism aware fetch policies for simultaneous multithreading processors. ACM Trans. Archit. Code Optim. 6(1): 3:1-3:33 (2009) - [j3]Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith:
A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27(2): 3:1-3:37 (2009) - [c8]Stijn Eyerman, Lieven Eeckhout:
Per-thread cycle accounting in SMT processors. ASPLOS 2009: 133-144 - [c7]Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout:
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. HiPEAC 2009: 110-124 - 2008
- [j2]Stijn Eyerman, Lieven Eeckhout:
System-Level Performance Metrics for Multiprogram Workloads. IEEE Micro 28(3): 42-53 (2008) - [c6]Stijn Eyerman, Lieven Eeckhout, James E. Smith:
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC 2008: 114-129 - 2007
- [j1]Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith:
A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro 27(1): 84-93 (2007) - [c5]Stijn Eyerman, Lieven Eeckhout, James E. Smith:
Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT 2007: 406 - [c4]Stijn Eyerman, Lieven Eeckhout:
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. HPCA 2007: 240-249 - 2006
- [c3]Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith:
A performance counter architecture for computing accurate CPI components. ASPLOS 2006: 175-184 - [c2]Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere:
Efficient design space exploration of high performance embedded out-of-order processors. DATE 2006: 351-356 - [c1]Stijn Eyerman, James E. Smith, Lieven Eeckhout:
Characterizing the branch misprediction penalty. ISPASS 2006: 48-58
Coauthor Index
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