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ORCIDAyan Mandal
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2020 – today
- 2023
[j1]Garima Modi
, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda:
CABARRE: Request Response Arbitration for Shared Cache Management. ACM Trans. Embed. Comput. Syst. 22(5s): 130:1-130:24 (2023)- [c12]Anush Niranjan Lingamoorthy, Amanda Watson, Korey Henderson, Ayan Mandal, David Gordon, Xiaonan Ma, James Weimer, Nagarajan Kandasamy, Jacob S. Brenner:
Dove: Shoulder-Based Opioid Overdose Detection and Reversal Device. CHASE 2023: 56-67
2010 – 2019
- 2013
- [c11]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Exploring topologies for source-synchronous ring-based network-on-chip. DATE 2013: 1026-1031 - [c10]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A source-synchronous Htree-based network-on-chip. ACM Great Lakes Symposium on VLSI 2013: 161-166 - [c9]Ayan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra:
A low-jitter phase-locked resonant clock generation and distribution scheme. ICCD 2013: 487-490 - 2012
- [c8]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean satisfiability using noise based logic. DAC 2012: 1260-1261 - [c7]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A fast, source-synchronous ring-based network-on-chip design. DATE 2012: 1489-1494 - [c6]Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri:
Alleviating NBTI-induced failure in off-chip output drivers. ACM Great Lakes Symposium on VLSI 2012: 295-298 - [c5]Rajeev Kumar, Ayan Mandal, Sunil P. Khatri:
An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. ICCD 2012: 195-200 - [c4]Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. ICCD 2012: 482-483 - 2011
- [c3]Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra:
An Automated Approach for Minimum Jitter Buffered H-Tree Construction. VLSI Design 2011: 76-81 - [c2]Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra:
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. VLSI Design 2011: 82-87 - [i1]Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri:
Boolean Satisfiability using Noise Based Logic. CoRR abs/1110.0550 (2011) - 2010
- [c1]Nikhil Gupta, Suman Kalyan Mandal, Javier Malave, Ayan Mandal, Rabi N. Mahapatra:
A Hardware Scheduler for Real Time Multiprocessor System on Chip. VLSI Design 2010: 264-269
Coauthor Index
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