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2020 – today
- 2024
[j17]Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani:
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 96-104 (2024)- [j16]Riaz-ul-haque Mian
, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michihiro Shintani:
Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(8): 1139-1150 (2024) - [c40]Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani:
EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing. DATE 2024: 1-6 - [c39]Yuta Shintani, Michiko Inoue, Michihiro Shintani:
Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process. DATE 2024: 1-6 - [c38]Michihiro Shintani, Takashi Sato:
(Invited) Redefining Outliers for On-Wafer Electrical Testing. MLCAD 2024: 39:1-39:7 - 2023
- [c37]Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani:
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. ASP-DAC 2023: 442-448 - [c36]Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani:
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. ITC 2023: 132-140 - [c35]Ayano Takaya, Michihiro Shintani:
Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique. ITC-Asia 2023: 1-6 - 2022
- [j15]Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato:
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5515-5525 (2022) - [c34]Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani:
Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data. ITC 2022: 573-577 - [i5]Kyohei Shimozato, Michihiro Shintani, Takashi Sato:
Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. CoRR abs/2201.10126 (2022) - [i4]Yuya Isaka, Michihiro Shintani, Foisal Ahmed, Michiko Inoue:
Systematic Unsupervised Recycled Field-Programmable Gate Array Detection. CoRR abs/2204.02159 (2022) - 2021
- [j14]Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Hardware-Software Co-Design for Decimal Multiplication. Comput. 10(2): 17 (2021) - [j13]Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1626-1639 (2021) - [c33]Michihiro Shintani, Mamoru Ishizaka, Michiko Inoue:
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network. ATS 2021: 25-30 - [c32]Yuya Isaka, Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation. IOLTS 2021: 1-6 - [c31]Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki:
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. ITC 2021: 103-112 - [c30]Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Study on High-Accuracy and Low-Cost Recycled FPGA Detection. ITC 2021: 133-142 - [i3]Michihiro Shintani, Aoi Ueda, Takashi Sato:
Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. CoRR abs/2110.15048 (2021) - [i2]Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue:
Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. CoRR abs/2111.01369 (2021) - 2020
- [j12]Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue:
Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit. J. Electron. Test. 36(4): 537-546 (2020) - [j11]Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1045-1053 (2020) - [c29]Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato:
Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. ATS 2020: 1-6 - [c28]Michihiro Shintani, Tomoki Mino, Michiko Inoue:
LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. ATS 2020: 1-6 - [c27]Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato:
Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. ATS 2020: 1-6 - [i1]Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. CoRR abs/2003.05315 (2020)
2010 – 2019
- 2019
- [c26]Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling. ETS 2019: 1-2 - [c25]Foisal Ahmed, Michihiro Shintani, Michiko Inoue:
Low Cost Recycled FPGA Detection Using Virtual Probe Technique. ITC-Asia 2019: 103-108 - [c24]Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue:
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. SoCC 2019: 412-417 - 2018
- [c23]Mian Riaz-ul-haque, Michihiro Shintani, Michiko Inoue:
Decimal Multiplication Using Combination of Software and Hardware. APCCAS 2018: 239-242 - [c22]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC 2018: 631-636 - [c21]Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue:
Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage. ATS 2018: 167-172 - [c20]Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED 2018: 251-256 - [c19]Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Variation-Aware Hardware Trojan Detection through Power Side-channel. ITC 2018: 1-10 - [c18]Michihiro Shintani, Michiko Inoue, Yoshiyuki Nakamura:
Artificial Neural Network Based Test Escape Screening Using Generative Model. ITC 2018: 1-8 - 2017
- [j10]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1464-1472 (2017) - [j9]Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2797-2806 (2017) - [c17]Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang:
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC 2017: 543-548 - [c16]Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu:
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS 2017: 52-57 - [c15]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC 2017: 66:1-66:6 - [c14]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED 2017: 426-431 - 2016
- [j8]Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato:
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. 32(5): 601-609 (2016) - [j7]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1400-1409 (2016) - [c13]Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato:
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS 2016: 234-239 - [c12]Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI 2016: 203-208 - [c11]Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato:
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED 2016: 307-312 - 2014
- [j6]Michihiro Shintani, Takashi Sato:
IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. IEICE Trans. Inf. Syst. 97-D(8): 2095-2104 (2014) - [j5]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato:
A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1056-1066 (2014) - [c10]Michihiro Shintani, Takashi Sato:
Sensorless estimation of global device-parameters based on Fmax testing. ICCAD 2014: 498-503 - 2013
- [j4]Michihiro Shintani, Takashi Sato:
Device-Parameter Estimation through IDDQ Signatures. IEICE Trans. Inf. Syst. 96-D(2): 303-313 (2013) - [c9]Michihiro Shintani, Takashi Sato:
An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC 2013: 614-619 - 2012
- [c8]Michihiro Shintani, Takashi Sato:
A Bayesian-based process parameter estimation using IDDQ current signature. VTS 2012: 86-91 - 2010
- [c7]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556 - [c6]Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato:
Path clustering for adaptive test. VTS 2010: 15-20
2000 – 2009
- 2009
- [c5]Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu:
An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156 - [c4]Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo:
Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS 2009: 27-32 - 2007
- [j3]Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue:
A Variable-Length Coding Adjustable for Compressed Test Application. IEICE Trans. Inf. Syst. 90-D(8): 1235-1242 (2007) - 2006
- [j2]Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
An Adaptive Decompressor for Test Application with Variable-Length Coding. Inf. Media Technol. 1(2): 909-917 (2006) - 2005
- [j1]Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue:
Huffman-Based Test Response Coding. IEICE Trans. Inf. Syst. 88-D(1): 158-161 (2005) - [c3]Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue:
A Huffman-based coding with efficient test application. ASP-DAC 2005: 75-78 - 2004
- [c2]Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
A Test Decompression Scheme for Variable-Length Coding. Asian Test Symposium 2004: 426-431 - 2003
- [c1]Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue:
Test Response Compression Based on Huffman Coding. Asian Test Symposium 2003: 446-451
Coauthor Index
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