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ORCIDSudhir S. Kudva
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2020 – today
- 2024
[c15]Siddharth Saxena, Sudhir S. Kudva, Vijay Srinivasan, Miguel Rodriguez, Walter Li, Shalimar Rasheed, Gaurav Ajwani, Tezaswi Raja, Santosh A, C. Thomas Gray:
A Distributed Power Supply Scheme with Dropout Voltage in Range 6mv-500mv and a Low Overhead Retention Mode. CICC 2024: 1-2- [c14]Sudhir S. Kudva, Mahmut Ersin Sinangil, Stephen G. Tell, Nikola Nedovic, Sanquan Song, Brian Zimmer, C. Thomas Gray:
16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking. ISSCC 2024: 302-304 - 2022
- [c13]Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray:
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. VLSI Technology and Circuits 2022: 146-147 - 2020
- [c12]Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC 2020: 126-128
2010 – 2019
- 2019
- [j3]John W. Poulton, John M. Wilson
, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54(1): 43-54 (2019) - [c11]Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - 2018
- [c10]Sudhir S. Kudva, Sanquan Song, John W. Poulton, John M. Wilson, Wenxu Zhao, C. Thomas Gray:
A switching linear regulator based on a fast-self-clocked comparator with very low probability of meta-stability and a parallel analog ripple control module. CICC 2018: 1-4 - [c9]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c8]John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC 2018: 276-278 - 2016
- [c7]Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun:
Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks. ASYNC 2016: 75-82 - 2014
- [c6]Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani:
High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. CICC 2014: 1-4 - 2013
- [j2]Sudhir S. Kudva, Ramesh Harjani:
Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. IEEE J. Solid State Circuits 48(8): 1910-1920 (2013) - 2012
- [c5]Sudhir S. Kudva, Ramesh Harjani:
Fully integrated capacitive converter with all digital ripple mitigation. CICC 2012: 1-4 - 2011
- [j1]Sudhir S. Kudva, Ramesh Harjani:
Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. IEEE J. Solid State Circuits 46(8): 1940-1951 (2011) - 2010
- [c4]Sudhir S. Kudva, Ramesh Harjani:
Fully integrated on-chip DC-DC converter with a 450x output range. CICC 2010: 1-4
2000 – 2009
- 2008
- [c3]Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva:
Quadrature generation techniques for frequency multiplication based oscillators. ISCAS 2008: 440-443 - 2007
- [c2]Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur:
A Low Power Frequency Multiplication Technique for ZigBee Transciever. VLSI Design 2007: 150-155 - 2004
- [c1]Aravind Al, Bindu P. Rao, Sudhir S. Kudva, Sreenu Babu, David S. Sumam, Ajit V. Rao:
Quality and complexity comparison of H.264 intra mode with JPEG2000 and JPEG. ICIP 2004: 525-528
Coauthor Index
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