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Tatsuyuki Ishikawa

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2000 – 2009

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2006
[j2]
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Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 969-978 (2006)
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Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3602-3612 (2006)
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Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto:
High-throughput decoder for low-density parity-check code. ASP-DAC 2006: 112-113
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Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule. ISCAS 2006
2005
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Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. ICCD 2005: 503-510

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