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Kiyoshi Takeuchi
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2020 – today
- 2020
- [c3]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto:
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309
2010 – 2019
- 2018
- [c2]Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai:
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC 2018: 26-29 - 2017
- [c1]Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi:
Parallel nonvolatile programming of power-up states of SRAM cells. ASICON 2017: 418-421 - 2012
- [j3]Kiyoshi Takeuchi:
Impact of Discrete-Charge-Induced Variability on Scaled MOS Devices. IEICE Trans. Electron. 95-C(4): 414-420 (2012) - 2011
- [j2]Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi:
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46(4): 806-814 (2011)
2000 – 2009
- 2007
- [j1]Katsuhiko Tanaka, Kiyoshi Takeuchi, Masami Hane:
Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices. IEICE Trans. Electron. 90-C(4): 842-847 (2007)
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