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2020 – today
- 2022
[c10]Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen:
Using deep learning models to predict student performance in introductory computer programming courses. ICALT 2022: 180-182- 2021
- [c9]Yueh-hui Vanessa Chiang, Ying-Zu Lin, Nian-Shing Chen:
An investigation of group, rater and ratee effects on peer-/self-assessments in a collaborative learning environment in higher education: a cross-classified multilevel analysis. ICALT 2021: 144-148 - [c8]Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu:
An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process. ISSCC 2021: 378-380
2010 – 2019
- 2019
- [c7]Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu:
A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET. ISSCC 2019: 330-332 - 2016
- [c6]Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu:
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j11]Chun-Cheng Liu, Che-Hsun Kuo, Ying-Zu Lin:
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. IEEE J. Solid State Circuits 50(11): 2645-2654 (2015) - 2014
- [c5]Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10b 100kS/s SAR ADC with charge recycling switching method. A-SSCC 2014: 329-332 - 2013
- [j10]Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, Soon-Jyh Chang:
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 570-581 (2013) - [j9]Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 584-588 (2013) - [j8]Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 624-635 (2013) - 2012
- [j7]Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, Soon-Jyh Chang:
A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2415-2423 (2012) - [j6]Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications. IEEE J. Solid State Circuits 47(11): 2783-2795 (2012) - 2011
- [c4]Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, Chun-Cheng Liu:
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. A-SSCC 2011: 69-72 - 2010
- [j5]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. IEEE J. Solid State Circuits 45(4): 731-740 (2010) - [j4]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1829-1837 (2010) - [j3]Ying-Zu Lin, Cheng-Wu Lin, Soon-Jyh Chang:
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 509-513 (2010) - [c3]Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai:
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. ISSCC 2010: 386-387
2000 – 2009
- 2009
- [j2]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu:
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process. IEICE Trans. Electron. 92-C(2): 258-268 (2009) - [c2]Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, Guan-Ying Huang:
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. ISSCC 2009: 80-81 - 2008
- [j1]Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu:
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1089-1093 (2008) - 2007
- [c1]Ying-Zu Lin, Yen-Ting Liu, Soon-Jyh Chang:
A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS. CICC 2007: 213-216
Coauthor Index
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