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2020 – today
- 2020
[j3]Gouhei Tanaka
, Ryosho Nakane, Tomoya Takeuchi, Toshiyuki Yamane, Daiju Nakano, Yasunao Katayama, Akira Hirose:
Spatially Arranged Sparse Recurrent Neural Networks for Energy Efficient Associative Memory. IEEE Trans. Neural Networks Learn. Syst. 31(1): 24-38 (2020)
2010 – 2019
- 2019
- [c31]Yasunao Katayama:
Channel Model for Spiking Neural Networks Inspired by Impulse Radio MIMO Transmission. GLOBECOM 2019: 1-6 - [i1]Yasunao Katayama:
Like Quantum Computing without Quantum Physics: Is it How the Brain Works? CoRR abs/1904.10508 (2019) - 2017
- [c30]Yasunao Katayama:
Brain-Inspired Memory Architecture for Sparse Nonlocal and Unstructured Workloads. Conf. Computing Frontiers 2017: 291-294 - 2015
- [c29]Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama:
Single-channel full-duplex mmWave link using phased-array for Ethernet. CCNC 2015: 400-405 - [c28]Toshiyuki Yamane, Yasunao Katayama, Ryosho Nakane, Gouhei Tanaka, Daiju Nakano:
Wave-Based Reservoir Computing by Synchronization of Coupled Oscillators. ICONIP (3) 2015: 198-205 - [c27]Gouhei Tanaka, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Yasunao Katayama:
Regularity and randomness in modular network structures for neural associative memories. IJCNN 2015: 1-7 - [c26]Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Gouhei Tanaka:
Wave-based device scaling concept for brain-like energy efficiency and integration. NANOARCH 2015: 23-24 - 2014
- [c25]Gouhei Tanaka, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Yasunao Katayama:
Hopfield-Type Associative Memory with Sparse Modular Networks. ICONIP (1) 2014: 255-262 - [c24]Nobuyuki Ohba, Seiji Munetoh, Atsuya Okazaki, Yasunao Katayama:
Non-intrusive Scalable Memory Access Tracer. QEST 2014: 245-248 - [c23]Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano:
An Energy-Efficient Computing Approach by Filling the Connectome Gap. UCNC 2014: 229-241 - [c22]Daiju Nakano, Yasuteru Kohda, Kohji Takano, Nobuyuki Ohba, Toshiyuki Yamane, Yasunao Katayama:
60-GHz single-carrier coherent detection system with robust 16-QAM signal recovery. WCNC 2014: 341-346 - 2013
- [c21]Yasunao Katayama, Atsuya Okazaki, Nobuyuki Ohba:
Software-defined massive multicore networking via freespace optical interconnect. Conf. Computing Frontiers 2013: 27:1-27:9 - 2012
- [c20]Nobuyuki Ohba, Kohji Takano, Yasuteru Kohda, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama:
Multimedia content-downloading system using millimeter-wave attached memory. CCNC 2012: 94-98 - [c19]Toshiyuki Yamane, Yasunao Katayama:
An effective initialization of interference cancellation algorithms for distributed MIMO systems in wireless datacenters. GLOBECOM 2012: 4249-4254 - [c18]Yasunao Katayama, Toshiyuki Yamane, Yasuteru Kohda, Kohji Takano, Daiju Nakano, Nobuyuki Ohba:
MIMO link design strategy for wireless data center applications. WCNC 2012: 3302-3306 - 2011
- [c17]Atsuya Okazaki, Yasunao Katayama, Seiji Munetoh:
Universal optical multi-drop bus for heterogeneous memory architecture. Conf. Computing Frontiers 2011: 16 - [c16]Daiju Nakano, Yasuteru Kohda, Kohji Takano, Toshiyuki Yamane, Nobuyuki Ohba, Yasunao Katayama:
Multi-Gbps 60-GHz single-carrier system using a low-power coherent detection technique. COOL Chips 2011: 1-3 - [c15]Yasuteru Kohda, Nobuyuki Ohba, Kohji Takano, Daiju Nakano, Toshiyuki Yamane, Yasunao Katayama:
Instant multimedia contents downloading system using a 60-GHZ-2.4-GHZ hybrid wireless link. ICME 2011: 1-6 - [c14]Yasunao Katayama, Kohji Takano, Yasuteru Kohda, Nobuyuki Ohba, Daiju Nakano:
Wireless data center networking with steered-beam mmWave links. WCNC 2011: 2179-2184
2000 – 2009
- 2008
- [c13]Yasunao Katayama, Daiju Nakano, Alberto Valdes-Garcia, Troy J. Beukema, Scott K. Reynolds:
Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections. ICME 2008: 513-516 - 2007
- [c12]Yasunao Katayama, Chuck Haymes, Daiju Nakano, Troy J. Beukema, Brian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Brian P. Gaucher, Kai Schleupen:
2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link. CCNC 2007: 12-16 - [c11]Yasunao Katayama, Atsuya Okazaki:
Optical Interconnect Opportunities for Future Server Memory Systems. HPCA 2007: 46-50 - 2006
- [c10]Yasunao Katayama, Daiju Nakano:
Multiple-Packet Recovery Technique using Partially-Overlapped Block Codes. ISIT 2006: 1978-1982 - 2003
- [c9]Toshiyuki Yamane, Yasunao Katayama:
An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability. ICASSP (2) 2003: 297-300 - [c8]Toshiyuki Yamane, Yasunao Katayama:
Bit error rate analysis on iterative two-stage decoding of two dimensional codes by importance sampling. ICC 2003: 3140-3144 - [c7]Toshiyuki Yamane, Yasunao Katayama:
An ultra-fast Reed-Solomon decoder soft-IP with 8-error correcting capability. ICME 2003: 445-448 - 2001
- [c6]Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane:
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). CAV 2001: 465-477 - 2000
- [c5]Yasunao Katayama, Yasushi Negishi, Sumio Morioka:
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. DFT 2000: 201- - [c4]Yasunao Katayama, Sumio Morioka:
One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. DSN 2000: 390-399
1990 – 1999
- 1999
- [c3]Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu:
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. DFT 1999: 311-318 - [c2]Sumio Morioka, Yasunao Katayama:
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. ICCD 1999: 60-67 - 1997
- [j2]Yasunao Katayama:
Trends in semiconductor memories. IEEE Micro 17(6): 10-17 (1997) - [c1]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285
1980 – 1989
- 1989
- [j1]Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano:
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE J. Solid State Circuits 24(5): 1198-1205 (1989)
Coauthor Index
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