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ORCIDMarcin Rogawski
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2010 – 2019
- 2016
[c10]Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski:
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. FPL 2016: 1-4- 2014
- [c9]Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk
, Marcin Rogawski, Marian Srebrny, Marcin Wójcik:
ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption. CHES 2014: 392-413 - [c8]Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj:
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs. FPL 2014: 1-8 - [i7]Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik:
ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption. IACR Cryptol. ePrint Arch. 2014: 266 (2014) - 2013
- [j2]Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol:
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl. Microprocess. Microsystems 37(6-7): 572-582 (2013) - 2012
- [c7]Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny:
Security Margin Evaluation of SHA-3 Contest Finalists through SAT-Based Attacks. CISIM 2012: 56-67 - [c6]Marcin Rogawski, Kris Gaj:
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl. DSD 2012: 568-575 - [i6]Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif:
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. IACR Cryptol. ePrint Arch. 2012: 368 (2012) - [i5]Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny:
Security margin evaluation of SHA-3 contest finalists through SAT-based attacks. IACR Cryptol. ePrint Arch. 2012: 421 (2012) - 2011
- [c5]Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj:
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. CHES 2011: 491-506 - [c4]Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj:
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates. FPT 2011: 1-9 - [c3]Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps:
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs. ReConFig 2011: 242-248 - [i4]Marcin Rogawski, Kris Gaj:
Groestl Tweaks and their Effect on FPGA Results. IACR Cryptol. ePrint Arch. 2011: 635 (2011) - 2010
- [j1]Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, Marcin Rogawski:
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve. IEEE Trans. Computers 59(9): 1264-1280 (2010) - [c2]Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski:
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. CHES 2010: 264-278 - [c1]Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster:
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs. FPL 2010: 414-421 - [i3]Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj:
Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs. IACR Cryptol. ePrint Arch. 2010: 445 (2010)
2000 – 2009
- 2003
- [i2]Marcin Rogawski:
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices. CoRR cs.CR/0312035 (2003) - [i1]Marcin Rogawski:
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices. IACR Cryptol. ePrint Arch. 2003: 258 (2003)
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