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ORCIDToshihiro Sekigawa
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2010 – 2019
- 2015
[j7]Yasuhiro Ogasahara
, Tadashi Nakagawa, Toshihiro Sekigawa, Toshiyuki Tsutsumi, Hanpei Koike:
Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. IEICE Electron. Express 12(15): 20150460 (2015)- 2013
- [c11]Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi:
Fully-functional FPGA prototype with fine-grain programmable body biasing. FPGA 2013: 73-80 - 2012
- [j6]Shin-ichi O'Uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. IEICE Trans. Electron. 95-C(4): 686-695 (2012) - [j5]Hideo Sakai, Shin-ichi O'Uchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara, Hiroki Ishikuro:
High-Frequency Precise Characterization of Intrinsic FinFET Channel. IEICE Trans. Electron. 95-C(4): 752-760 (2012) - 2010
- [c10]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. CICC 2010: 1-4 - [c9]Shin-ichi O'Uchi, Kazuhiko Endo, Yongxun Liu, Tadashi Nakagawa, Takashi Matsukawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara:
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. ESSCIRC 2010: 474-477
2000 – 2009
- 2008
- [j4]Shin-ichi O'Uchi, Meishoku Masahara, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Kunihiro Sakamoto, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. IEICE Trans. Electron. 91-C(4): 534-542 (2008) - [j3]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa:
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ACM Trans. Reconfigurable Technol. Syst. 1(1): 3:1-3:31 (2008) - 2007
- [j2]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. IEICE Trans. Inf. Syst. 90-D(12): 1947-1955 (2007) - [c8]Shin-ichi O'Uchi, Meishoku Masahara, Kunihiro Sakamoto, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki:
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. CICC 2007: 33-36 - [c7]Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. FPGA 2007: 169-177 - [c6]Masakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi:
A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. FPT 2007: 285-288 - 2006
- [c5]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPGA 2006: 223 - [c4]Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Evaluation of granularity on threshold voltage control in flex power FPGA. FPT 2006: 17-24 - [c3]Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Optimal set of body bias voltages for an FPGA with field-programmable Vth components. FPT 2006: 329-332 - 2005
- [c2]Hanpei Koike, Toshihiro Sekigawa:
XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together. CICC 2005: 247-250 - 2004
- [j1]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. IEICE Trans. Inf. Syst. 87-D(8): 2004-2010 (2004) - [c1]Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257
Coauthor Index
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