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2020 – today
- 2025
[c26]Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne
:
FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. FPGA 2025: 147-158- 2024
- [j9]Dina G. Mahmoud, Beatrice Shokry, Vincent Lenders, Wei Hu, Mirjana Stojilovic:
X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs. IEEE Access 12: 8983-9011 (2024) - 2023
- [j8]Dina G. Mahmoud, Vincent Lenders, Mirjana Stojilovic:
Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era. ACM Comput. Surv. 55(3): 58:1-58:40 (2023) - [j7]Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic:
The Side-channel Metrics Cheat Sheet. ACM Comput. Surv. 55(10): 216:1-216:38 (2023) - [j6]Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilovic:
Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs. J. Hardw. Syst. Secur. 7(2): 72-99 (2023) - [j5]Mirjana Stojilovic, Kasper Rasmussen, Francesco Regazzoni, Mehdi B. Tahoori, Russell Tessier:
A Visionary Look at the Security of Reconfigurable Cloud Computing. Proc. IEEE 111(12): 1548-1571 (2023) - [j4]David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic:
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(2): 543-567 (2023) - [c25]Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic:
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. DATE 2023: 1-6 - [c24]Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic:
Active Wire Fences for Multitenant FPGAs. DDECS 2023: 13-20 - [c23]Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA 2023: 231 - [c22]Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson:
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL 2023: 305-310 - [c21]Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD 2023: 1-9 - [i4]David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic:
RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Cryptol. ePrint Arch. 2023: 43 (2023) - 2022
- [j3]Dina G. Mahmoud, David Dervishi, Samah Hussein, Vincent Lenders, Mirjana Stojilovic:
DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks. IEEE Access 10: 134199-134216 (2022) - [c20]Hedi Fendri, Marco Macchetti, Jérôme Perrine, Mirjana Stojilovic:
A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time. DATE 2022: 670-675 - [c19]Dina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic:
FPGA-to-CPU Undervolting Attacks. DATE 2022: 999-1004 - [i3]Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic:
The Side-Channel Metric Cheat Sheet. IACR Cryptol. ePrint Arch. 2022: 253 (2022) - 2021
- [j2]Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access 9: 115599-115619 (2021) - [c18]Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic:
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks. DATE 2021: 1645-1650 - [c17]Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic:
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs. FPGA 2021: 11-22 - [c16]Olivia Jullian, Beatriz Otero, Mirjana Stojilovic, Juan José Costa, Javier Verdú, Manuel Alejandro Pajuelo:
Deep Learning Detection of GPS Spoofing. LOD 2021: 527-540 - 2020
- [c15]Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic:
Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? DATE 2020: 1007-1010 - [c14]Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic:
Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. FPGA 2020: 197-203 - [c13]Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic:
Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. FPGA 2020: 204-210 - [c12]Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic:
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. FPGA 2020: 317 - [c11]Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic:
X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. FPL 2020: 185-192 - [c10]Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic:
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. FPT 2020: 288-289 - [c9]Frédéric Gessler, Philip Brisk, Mirjana Stojilovic:
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSID 2020: 78-83 - [i2]Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic:
Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. IACR Cryptol. ePrint Arch. 2020: 1494 (2020) - [i1]Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic:
CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. IACR Cryptol. ePrint Arch. 2020: 1495 (2020)
2010 – 2019
- 2019
- [c8]Dina Mahmoud, Mirjana Stojilovic:
Timing Violation Induced Faults in Multi-Tenant FPGAs. DATE 2019: 1745-1750 - [c7]Dario Korolija, Mirjana Stojilovic:
Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform. FPGA 2019: 186 - [c6]Seyedeh Sharareh Mirzargar, Mirjana Stojilovic:
Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. FPL 2019: 202-210 - [c5]Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT 2019: 10-18 - [c4]Dario Korolija, Mirjana Stojilovic:
FPGA-Assisted Deterministic Routing for FPGAs. IPDPS Workshops 2019: 155-162 - 2018
- [c3]Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk:
Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL 2018: 21-25 - 2017
- [c2]Mirjana Stojilovic:
Parallel FPGA routing: Survey and challenges. FPL 2017: 1-8 - 2013
- [j1]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - 2012
- [c1]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548
Coauthor Index
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