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ORCIDShaishav Desai
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2020 – today
- 2024
[c10]Ping Lu, Minhan Chen, Shaishav Desai:
A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC. ISCAS 2024: 1-5- 2022
- [c9]Ping Lu, Minhan Chen, Shaishav Desai:
An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications. MWSCAS 2022: 1-4 - 2021
- [j2]Eric Groen
, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai:
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture. IEEE J. Solid State Circuits 56(1): 30-42 (2021) - [j1]Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai:
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET. IEEE J. Solid State Circuits 56(4): 1265-1277 (2021) - 2020
- [c8]Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Nhat Nguyen, Shaishav Desai:
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET. ISSCC 2020: 120-122 - [c7]Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai:
A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET. VLSI Circuits 2020: 1-2
2010 – 2019
- 2014
- [c6]Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung:
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. CICC 2014: 1-4 - 2012
- [c5]Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung:
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. ESSCIRC 2012: 458-461 - [c4]Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, Kuo-Chiang Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang, Jason Yeung, Khaldoon Abugharbieh, Ying Cao:
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications. MWSCAS 2012: 5-8
2000 – 2009
- 2009
- [c3]Chethan Rao, Alvin Wang, Shaishav Desai:
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes. CICC 2009: 239-242 - 2007
- [c2]Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong:
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. ISSCC 2007: 104-105 - [c1]Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael:
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. ISSCC 2007: 308-605
Coauthor Index
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