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2010 – 2019
- 2012
[j1]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Sohn, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. IEEE J. Solid State Circuits 47(1): 131-140 (2012)- 2011
- [c2]Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. ISSCC 2011: 502-504
2000 – 2009
- 2009
- [c1]Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung:
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. ISSCC 2009: 140-141
Coauthor Index
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