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2020 – today
- 2022
[c12]Cristina Laura Sîrbu, Ciprian Seiculescu, Ghita Adrian Burdan, Tudor Moga, Catalin-Daniel Caleanu:
Evaluation of Tracking Algorithms for Contrast Enhanced Ultrasound Imaging Exploration. ACSW 2022: 161-167- [c11]Ioan Lucan Orasan, Ciprian Seiculescu, Catalin-Daniel Caleanu:
Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks. SACI 2022: 221-226
2010 – 2019
- 2013
- [j3]Ciprian Seiculescu, Dara Rahmati
, Srinivasan Murali, Hamid Sarbazi-Azad, Luca Benini, Giovanni De Micheli:
Designing best effort networks-on-chip to meet hard latency constraints. ACM Trans. Embed. Comput. Syst. 12(4): 108:1-108:23 (2013) - [c10]Shashikanth Bobba, Pierre-Emmanuel Gaillardon, Ciprian Seiculescu, Vasilis F. Pavlidis, Giovanni De Micheli:
3.5-D integration: A case study. ISCAS 2013: 2087-2090 - 2012
- [b1]Ciprian Seiculescu:
Design Methods and Tools for Application-Specific Predictable Networks-on-Chip. EPFL, Switzerland, 2012 - [c9]Ciprian Seiculescu, Luca Benini, Giovanni De Micheli:
A distributed interleaving scheme for efficient access to WideIO DRAM memory. CODES+ISSS 2012: 103-112 - [c8]Stavros Volos, Ciprian Seiculescu, Boris Grot, Naser Khosro Pour, Babak Falsafi, Giovanni De Micheli:
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers. NOCS 2012: 67-74 - 2011
- [c7]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
A DRAM Centric NoC Architecture and Topology Design Approach. ISVLSI 2011: 54-59 - [p2]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs. Low Power Networks-on-Chip 2011: 199-222 - [p1]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks. 3D Integration for NoC-based SoC Architectures 2011: 193-223 - 2010
- [j2]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1987-2000 (2010) - [j1]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 364-368 (2010) - [c6]Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini:
Networks on Chips: from research to products. DAC 2010: 300-305 - [c5]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. DATE 2010: 1625-1628
2000 – 2009
- 2009
- [c4]Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli:
Synthesis of networks on chips for 3D systems on chips. ASP-DAC 2009: 242-247 - [c3]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
NoC topology synthesis for supporting shutdown of voltage islands in SoCs. DAC 2009: 822-825 - [c2]Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. DATE 2009: 9-14 - [c1]Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini:
A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC 2009: 379-382
Coauthor Index
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