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2020 – today
- 2023
[c61]Ze Yang, Yimeng Sun, Takao Nakaguchi, Masaharu Imai:
EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information. ICKG 2023: 142-151
2010 – 2019
- 2018
- [j27]Koichi Mitsunari, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu:
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(11): 1766-1775 (2018) - 2017
- [j26]Yuuka Hirao, Yoshinori Takeuchi, Masaharu Imai, Jaehoon Yu:
Deformable Part Model Based Arrhythmia Detection Using Time Domain Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(11): 2221-2229 (2017) - [j25]Tomoki Sugiura, Masaharu Imai, Jaehoon Yu, Yoshinori Takeuchi:
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems. J. Inf. Process. 25: 210-219 (2017) - [c60]Masaharu Imai, Yoshinori Takeuchi, Jun Ohta, Gregg Jørgen Suaning, Chung-Yu Wu, Napoleon Torres-Martinez
:
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface. ASP-DAC 2017: 299 - [c59]Fumika Tanabe, Shusuke Yoshimoto, Yuki Noda, Teppei Araki, Takafumi Uemura, Yoshinori Takeuchi, Masaharu Imai, Tsuyoshi Sekitani:
Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty. EMBC 2017: 1591-1594 - 2016
- [c58]Tomoki Sugiura, Arif Ullah Khan, Jaehoon Yu, Yoshinori Takeuchi, Seiji Kameda, Takatsugu Kamata, Yuki Hayashida, Tetsuya Yagi, Masaharu Imai:
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis. BioCAS 2016: 432-435 - 2015
- [j24]Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai:
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. Inf. Media Technol. 10(2): 192-203 (2015) - [j23]Salita Sombatsiri, Yoshinori Takeuchi, Masaharu Imai:
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC. IPSJ Trans. Syst. LSI Des. Methodol. 8: 26-37 (2015) - [c57]Tomoki Sugiura, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai:
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems. BioCAS 2015: 1-4 - [c56]Yuki Hayashida, Yuichi Umehira, Kouki Takatani, Shigetoshi Futami, Seiji Kameda, Takatsugu Kamata, Arif Ullah Khan, Yoshinori Takeuchi, Masaharu Imai, Tetsuya Yagi:
Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system. EMBC 2015: 1642-1645 - [c55]Toshiyo Tamura, Masaki Sekine, Zunyi Tang, Masaki Yoshida, Yoshinori Takeuchi, Masaharu Imai:
Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke. EMBC 2015: 5489-5492 - 2014
- [j22]Masaharu Imai, Yoshio Sugizaki, Koichi Asatani:
A New Available Bandwidth Estimation Method Using RTT for a Bottleneck Link. IEICE Trans. Commun. 97-B(4): 712-720 (2014) - [c54]Tomoki Sugiura, Shoko Nakatsuka, Jaehoon Yu, Yoshinori Takeuchi, Masaharu Imai:
An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology. BioCAS 2014: 81-84 - 2013
- [j21]Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka:
Electronic triage system for continuously monitoring casualties at disaster scenes. J. Ambient Intell. Humaniz. Comput. 4(5): 547-558 (2013) - [c53]Masaharu Imai, Takayuki Ozawa, Yoshio Sugizaki, Koichi Asatani:
Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link. APNOMS 2013: 1-3 - [c52]Shoko Nakatsuka, Takashi Hamabe, Yoshinori Takeuchi, Masaharu Imai:
An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology. BioCAS 2013: 382-385 - [c51]Masaharu Imai, Yoshio Sugizaki, Koichi Asatani:
A new estimation method using RTT for available bandwidth of a bottleneck link. ICOIN 2013: 529-534 - 2012
- [j20]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. IEICE Trans. Electron. 95-C(4): 487-494 (2012) - [c50]Salita Sombatsiri, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
On-chip Communication Buffer Architecture Optimization Considering Bus Width. MCSoC 2012: 29-36 - [c49]Sho Ninomiya, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. MCSoC 2012: 107-112 - 2011
- [j19]Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2659-2668 (2011) - [c48]Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka:
Electronic Triage System: Casualties Monitoring System in the Disaster Scene. 3PGCIC 2011: 317-322 - [c47]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato:
Biological information sensing technologies for medical, health care, and wellness applications. ASP-DAC 2011: 551-555 - [c46]Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Automated architecture exploration for low energy reconfigurable AGU. ISOCC 2011: 191-194 - 2010
- [j18]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). Inf. Media Technol. 5(4): 1064-1081 (2010) - [j17]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. Inf. Media Technol. 5(4): 1110-1121 (2010) - [j16]Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Nagisa Ishiura:
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). IPSJ Trans. Syst. LSI Des. Methodol. 3: 161-178 (2010) - [j15]Takahiro Kumura, Soichiro Taga, Nagisa Ishiura, Yoshinori Takeuchi, Masaharu Imai:
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors. IPSJ Trans. Syst. LSI Des. Methodol. 3: 207-221 (2010) - [j14]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 3: 222-233 (2010) - [c45]Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai:
A new compilation technique for SIMD code generation across basic block boundaries. ASP-DAC 2010: 101-106 - [c44]Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Two-stage configurable decoder model for multiple forward error correction standards. ESTIMedia 2010: 114-120 - [c43]Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. ISCAS 2010: 3729-3732
2000 – 2009
- 2009
- [j13]Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moniem Wahdan, Masaharu Imai:
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1088-1095 (2009) - [j12]Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai:
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1161-1173 (2009) - [j11]Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3258-3267 (2009) - [c42]Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. ASP-DAC 2009: 449-454 - 2008
- [j10]Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 604-612 (2008) - [c41]Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Operation shuffling over cycle boundaries for low energy L0 clustering. ASAP 2008: 150-155 - 2007
- [j9]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto:
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2800-2809 (2007) - [j8]Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. ACM Trans. Design Autom. Electr. Syst. 12(4): 41 (2007) - [c40]Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ASP-DAC 2007: 286-291 - [c39]Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
A low power VLIW processor generation method by means of extracting non-redundant activation conditions. CODES+ISSS 2007: 227-232 - [c38]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Shiro Kobayashi:
A Block-Floating-Point Processor for Rapid Application Development. ICASSP (2) 2007: 65-68 - [i1]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. CoRR abs/0710.4746 (2007) - 2006
- [c37]Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa:
Pack instruction generation for media pUsing multi-valued decision diagram. CODES+ISSS 2006: 154-159 - [c36]Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. VLSI-SoC 2006: 290-295 - [c35]Ittetsu Taniguchi, Keishi Sakanushi, Kyoko Ueda, Yoshinori Takeuchi, Masaharu Imai:
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. VLSI-SoC (Selected Papers) 2006: 357-376 - 2005
- [c34]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Enabling RTOS simulation modeling in a system level design language. ASP-DAC 2005: 936-939 - [c33]Masaharu Imai, Akira Kitajima:
Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME 2005: 2 - [c32]M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. DATE 2005: 554-559 - [c31]Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai:
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. ESTIMedia 2005: 81-86 - [e2]Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic:
Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-53-X [contents] - 2004
- [c30]Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Synthesizable HDL generation method for configurable VLIW processors. ASP-DAC 2004: 842-845 - [c29]Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Architecture-Level Performance Estimation for IP-Based Embedded Systems. DATE 2004: 1002-1007 - [c28]H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. ICDCS Workshops 2004: 824-830 - [c27]Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai:
S-sequence: a new floorplan representation method preserving room abutment relationships. ISCAS (4) 2004: 505-508 - [e1]Masaharu Imai:
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004. IEEE Computer Society 2004, ISBN 0-7803-8175-0 [contents] - 2003
- [j7]Masaharu Imai:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2913 (2003) - [c26]Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai:
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICASSP (2) 2003: 485-488 - [c25]Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai:
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III. ICME 2003: 149-152 - [c24]Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai:
A Code Selection Method for SIMD Processors with PACK Instructions. SCOPES 2003: 66-80 - 2002
- [j6]Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai:
A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2586-2595 (2002) - [c23]Shinsuke Kobayashi, Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai:
Design space exploration for DSP applications using the ASIP development system PEAS-III. ICASSP 2002: 3168-3171 - [c22]Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai:
Design of Application Specific CISC Using PEAS-III. IEEE International Workshop on Rapid System Prototyping 2002: 12-17 - 2001
- [c21]Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai:
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ASP-DAC 2001: 649-654 - [c20]Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai:
VLSI Implementation of Fractal Image Compression Processor for Moving Pictures. EUROMICRO 2001: 400-409 - 2000
- [c19]Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura:
One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654 - [c18]Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi:
PEAS-III: An ASIP Design Environment. ICCD 2000: 430-436
1990 – 1999
- 1999
- [c17]Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura:
Application of FHM-Based Design Method to Scalable 2-D DCT Processor. EUROMICRO 1999: 1406-1409 - [c16]Takafumi Morifuji, Yoshinori Takeuchi, Masaharu Imai:
A programmable processor with multiple functional units and banked registers for general purpose numerical processing. ICASSP 1999: 1985-1988 - 1998
- [c15]Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi:
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes. ASP-DAC 1998: 367-372 - 1997
- [c14]Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai:
VLSI implementation of a real-time operating system. ASP-DAC 1997: 679-680 - 1996
- [j5]Masaharu Imai, Eugenio Villar:
ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. 13(1): 3-4 (1996) - [j4]Takumi Nakano, Andy Utama, Akichika Shiomi, Masaharu Imai, Mitsuyoshi Itabashi:
VLSI implementation and evaluation of a real-time operating system. Syst. Comput. Jpn. 27(6): 1-10 (1996) - [c13]Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC 1996: 527-532 - [c12]Masaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi:
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs. EURO-DAC 1996: 126-131 - 1995
- [c11]Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC 1995 - [c10]Masaharu Imai, Eugenio Villar:
Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC 1995 - [c9]Eugenio Villar, Masaharu Imai:
Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC 1995 - [c8]Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi:
A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC 1995: 176-181 - 1993
- [c7]Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai:
PEAS-I: A hardware/software co-design system for ASIPs. EURO-DAC 1993: 2-7 - [c6]Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi:
An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD 1993: 526-532 - 1992
- [c5]Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi:
An integer programming approach to instruction implementation method selection problem. EURO-DAC 1992: 106-111 - 1991
- [c4]Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi:
An Integrated Design Environment for Application Specific Integrated Processor. ICCD 1991: 414-417
1980 – 1989
- 1988
- [j3]Yoshinao Suzuki, Tomio Hirata, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki:
Reconfiguration of a fault-tolerant rectangular systolic array. Syst. Comput. Jpn. 19(1): 79-89 (1988) - [j2]Hiroshi Yamasaki, Tomio Hirata, Masaharu Imai, Toshihide Ibaraki:
Computational complexity of the file allocation problem in distributed database systems. Syst. Comput. Jpn. 19(3): 53-63 (1988) - 1987
- [j1]Hiromoto Usui, Masafumi Yamashita, Masaharu Imai, Toshihide Ibaraki:
Parallel searches of game trees. Syst. Comput. Jpn. 18(8): 97-109 (1987) - 1986
- [c3]Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki:
Implementation of Parallel Prolog on Tree Machines. FJCC 1986: 287-296 - 1984
- [c2]Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura:
The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System. ICDCS 1984: 174-182
1970 – 1979
- 1979
- [c1]Masaharu Imai, Yuuji Yoshida, Teruo Fukumura:
A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems. IJCAI 1979: 416-418
Coauthor Index
[j27] [j26] [j25] [c60] [c59] [c58] [j24] [j23] [c57] [c56] [c55] [c54] [j21] [c52] [j20] [c50] [c49] [j19] [c48] [c47] [c46] [j18] [j17] [j16] [j15] [j14] [c45] [c44] [c43] [j13] [j12] [j11] [c42] [j9] [c40] [c39] [c38] [i1] [c37] [c36] [c35] [c34] [c32] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [j6] [c23] [c22] [c21] [c20] [c18] [c17] [c16] [c15]
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