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2010 – 2019
- 2019
[c17]Chiara Sandionigi, Olivier Héron:
Estimation of oxide breakdown effects by fault injection. IOLTS 2019: 269-274- 2017
- [c16]Chiara Sandionigi, Maurício Altieri, Olivier Héron:
Early estimation of aging in the design flow of integrated circuits through a programmable hardware module. DFT 2017: 1-6 - 2016
- [c15]Boukary Ouattara, Olivier Héron, Chiara Sandionigi:
Fine-grain analysis of the parameters involved in aging of digital circuits. IOLTS 2016: 51-53 - 2015
- [c14]Chiara Sandionigi, Olivier Héron:
Identifying aging-aware representative paths in processors. IOLTS 2015: 32-33 - [c13]Olivier Héron, Chiara Sandionigi, E. Piriou, Safa Mbarek, Vincent Huard:
Workload-dependent BTI analysis in a processor core at high level. IRPS 2015: 6 - [c12]Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Julien Mottin, Pascal Vivet
, Hela Boussetta, Nicolas Peltier:
A simulation framework for rapid prototyping and evaluation of thermal mitigation techniques in many-core architectures. ISLPED 2015: 25-30 - 2014
- [j6]Cristiana Bolchini, Chiara Sandionigi:
Design of Hardened Embedded Systems on Multi-FPGA Platforms. ACM Trans. Design Autom. Electr. Syst. 20(1): 16:1-16:26 (2014) - [c11]Tanguy Sassolas, Chiara Sandionigi, Alexandre Guerre, Alexandre Aminot, Pascal Vivet, Hela Boussetta, Luca Ferro, Nicolas Peltier:
Early design stage thermal evaluation and mitigation: The locomotiv architectural case. DATE 2014: 1-2 - 2013
- [j5]Olivier Héron, Clement Bertolini, Chiara Sandionigi, Nicolas Ventroux, François Marc:
On the Simulation of HCI-Induced Variations of IC Timings at High Level. J. Electron. Test. 29(2): 127-141 (2013) - [j4]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms. J. Electron. Test. 29(6): 779-793 (2013) - [j3]Chiara Sandionigi, Danilo Ardagna, Gianpaolo Cugola, Carlo Ghezzi:
Optimizing Service Selection and Allocation in Situational Computing Applications. IEEE Trans. Serv. Comput. 6(3): 414-428 (2013) - [c10]Chiara Sandionigi, Olivier Héron, Clement Bertolini, Raphaël David:
When processors get old: Evaluation of BTI and HCI effects on performance and reliability. IOLTS 2013: 185-186 - 2012
- [b1]Chiara Sandionigi:
A reliability-aware design methodology for embedded systems on multi-FPGA platforms. Polytechnic University of Milan, Italy, 2012 - [c9]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, Marta Bagatin, Alessandro Paccagnella:
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. DFT 2012: 121-125 - [c8]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
Increasing autonomous fault-tolerant FPGA-based systems' lifetime. ETS 2012: 1-6 - 2011
- [j2]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs. IEEE Trans. Computers 60(12): 1744-1758 (2011) - [c7]Cristiana Bolchini, Chiara Sandionigi:
A Reliability-Aware Partitioner for Multi-FPGA Platforms. DFT 2011: 34-40 - [c6]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi:
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems. FPL 2011: 532-538 - [c5]Cristiana Bolchini, Chiara Sandionigi, Luca Fossati, David Merodio Codinachs:
A reliable fault classifier for dependable systems on SRAM-based FPGAs. IOLTS 2011: 92-97 - 2010
- [j1]Cristiana Bolchini, Chiara Sandionigi:
Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation. IEEE Embed. Syst. Lett. 2(4): 107-110 (2010) - [c4]Cristiana Bolchini, Luca Fossati, David Merodio Codinachs, Antonio Miele, Chiara Sandionigi:
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms. DFT 2010: 191-199 - [c3]Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante:
An integrated flow for the design of hardened circuits on SRAM-based FPGAs. ETS 2010: 214-219
2000 – 2009
- 2007
- [c2]Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation. VLSI-SoC (Selected Papers) 2007: 1-18 - [c1]Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation. VLSI-SoC 2007: 128-133
Coauthor Index
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