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2010 – 2019
- 2016
[j13]Kohei Sugiyama, Takayuki Matsuno, Tetsushi Kamegawa, Takao Hiraki, Hirotaka Nakaya, Masayuki Nakamura, Akira Yanou, Mamoru Minami:
Needle Tip Position Accuracy Evaluation Experiment for Puncture Robot in Remote Center Control. J. Robotics Mechatronics 28(6): 911-920 (2016)- 2015
- [c9]Masayuki Nakamura, Takashi Yoshikawa, Kayo Tanaka, Mengyuan Liao, Noriaki Kuwahara:
The Digital Reminiscence Method: Effect on Dementia in Japanese Day Care Centers. HCI (17) 2015: 482-489 - 2014
- [c8]Hideaki Hashimoto, Keigo Matsuo, Kazuaki Chikira, Masayuki Nakamura, Joji Urata:
Energy-aware resource management of virtual machines under thermal and placement constraints. IGCC 2014: 1-7 - 2012
- [c7]Takayuki Nakamura, Yukio Kikuya, Yutaka Arakawa, Motonori Nakamura, Yuka Higashijima, Yasuko Yamada Maruo, Masayuki Nakamura:
Proposal of Web Framework for Ubiquitous Sensor Network and Its Trial Application Using NO2 Sensor Mounted on Bicycle. SAINT 2012: 83-90 - 2011
- [j12]Masayuki Nakamura, Jiro Nakamura, Guillaume Lopez
, Masaki Shuzo, Ichiro Yamada:
Collaborative Processing of Wearable and Ambient Sensor System for Blood Pressure Monitoring. Sensors 11(7): 6760-6770 (2011)
2000 – 2009
- 2009
- [j11]Masayuki Nakamura, Atsushi Sakurai, Jiro Nakamura:
Distributed Environment Control Using Wireless Sensor/Actuator Networks for Lighting Applications. Sensors 9(11): 8593-8609 (2009) - 2008
- [j10]Masayuki Nakamura, Shoshin Kubota, Hideaki Takagi, Kiyoshi Einaga, Masashi Yokoyama, Katsuto Mochizuki, Masaomi Takizawa, Sumio Murase:
Development of Long-Range and High-Speed Wireless LAN for the Transmission of Telemedicine from Disaster Areas. EURASIP J. Wirel. Commun. Netw. 2008 (2008) - [j9]Masayuki Nakamura, Atsushi Sakurai, Shizuo Furubo, Hiroshi Ban:
Collaborative processing in Mote-based sensor/actuator networks for environment control application. Signal Process. 88(7): 1827-1838 (2008) - [c6]Masayuki Nakamura, Atsushi Sakurai, Takumi Yamada, Jiro Nakamura:
Adaptive sensor/actuator networks for tracking environment control behaviors. CSTST 2008: 682-687 - 2007
- [j8]Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. IEEE J. Solid State Circuits 42(1): 201-209 (2007) - 2006
- [c5]Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. ISSCC 2006: 557-566 - [c4]Masayuki Nakamura, Atsushi Sakurai, Toshio Watanabe, Jiro Nakamura, Hiroshi Ban:
Improved Collaborative Environment Control Using Mote-based Sensor/Actuator Networks. LCN 2006: 561-562 - 2005
- [j7]Hiroki Fujisawa, Masayuki Nakamura, Yasuhiro Takai, Yasuji Koshikawa, Tatsuya Matano, Seiji Narui, Narikazu Usuki, Chiaki Dono, Shinichi Miyatake, Makoto Morino, Koji Arai, Shuichi Kubouchi, Isamu Fujii, Hideyuki Yoko, Takao Adachi:
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer. IEEE J. Solid State Circuits 40(4): 862-869 (2005) - [c3]Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso:
Is methodology the highway out of verification hell? DAC 2005: 521-522 - 2004
- [j6]Masayuki Nakamura, Hiroki Nomiya, Kuniaki Uehara:
Improvement of Boosting Algorithm by Modifying the Weighting Rule. Ann. Math. Artif. Intell. 41(1): 95-109 (2004) - 2003
- [j5]Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama:
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. IEEE J. Solid State Circuits 38(5): 762-768 (2003) - [c2]Masayuki Nakamura, Yuying Yang, Katsumi Wasaki, Yasunari Shidama:
Study on a noise reduction system of CATV network upstream for data communication. ICCCN 2003: 613-616 - 2002
- [j4]Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37(4): 487-498 (2002) - [c1]Masayuki Nakamura, Kuniaki Uehara:
Improvement of Boosting Algorithm by Modifying the Weighting Rule. AI&M 2002 - 2001
- [j3]Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya:
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. IEEE J. Solid State Circuits 36(7): 1120-1126 (2001) - [j2]Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36(11): 1721-1727 (2001)
1990 – 1999
- 1996
- [j1]Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato:
A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J. Solid State Circuits 31(9): 1302-1307 (1996)
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