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ORCIDRajat Chaudhry
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2000 – 2009
- 2006
[j2]Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006)- [c6]Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posluszny, Sang H. Dhong:
A cycle accurate power estimation tool. ASP-DAC 2006: 867-870 - 2005
- [j1]Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang:
Cell Processor Low-Power Design Methodology. IEEE Micro 25(6): 71-78 (2005) - 2000
- [c5]Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw:
Hierarchical analysis of power distribution networks. DAC 2000: 150-155 - [c4]Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards:
Current signature compression for IR-drop analysis. DAC 2000: 162-167 - [c3]Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju:
Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184 - [c2]Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw:
Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155
1990 – 1999
- 1998
- [c1]Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns:
Area-oriented synthesis for pass-transistor logic. ICCD 1998: 160-167
Coauthor Index
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