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2010 – 2019
- 2017
[c24]Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang:
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. ISCAS 2017: 1-4- 2016
- [c23]Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. ICICDT 2016: 1-4 - [c22]Vita Pi-Ho Hu
, Pin Su, Ching-Te Chuang:
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ISCAS 2016: 2106-2109 - [c21]Chang-Hung Yu, Pin Su, Ching-Te Chuang:
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. ISLPED 2016: 242-247 - 2015
- [j7]Ko-Chun Lee, Ming-Long Fan, Pin Su:
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation. Microelectron. Reliab. 55(2): 332-336 (2015) - [c20]Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ICICDT 2015: 1-4 - [c19]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ISCAS 2015: 601-604 - [c18]Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ISCAS 2015: 2325-2328 - [c17]Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC 2015: 339-344 - 2014
- [j6]Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 389-399 (2014) - [j5]Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron. Reliab. 54(4): 698-711 (2014) - [j4]Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3339-3347 (2014) - [c16]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. ISCAS 2014: 1122-1125 - [c15]Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. ISCAS 2014: 1130-1133 - [c14]Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. ISLPED 2014: 255-258 - 2013
- [c13]Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. ICICDT 2013: 61-64 - [c12]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. ISQED 2013: 347-352 - 2012
- [j3]Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 878-882 (2012) - [j2]Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1201-1210 (2012) - [c11]Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. APCCAS 2012: 463-466 - [c10]Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. APCCAS 2012: 471-474 - [c9]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. ESSDERC 2012: 77-80 - [c8]Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang:
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. ESSDERC 2012: 157-160 - [c7]Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. ICICDT 2012: 1-4 - 2011
- [j1]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 335-342 (2011) - [c6]Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Analysis of power-performance for ultra-thin-body GeOI logic circuits. ISLPED 2011: 115-120
2000 – 2009
- 2009
- [c5]Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ISLPED 2009: 9-14 - 2003
- [c4]Pin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu:
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. CICC 2003: 241-244 - 2002
- [c3]Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu:
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ISQED 2002: 487-491 - 2001
- [c2]Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu:
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. CICC 2001: 381-384 - 2000
- [c1]Pin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu:
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. CICC 2000: 197-200
Coauthor Index
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