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2020 – today
- 2021
[c15]Jérémy Foxcroft, Tianle Chen, Kanchana Padmanabhan, Brian Keng, Luiza Antonie:
Product Matching Lessons and Recommendations from a Real World Application. Canadian AI 2021
2010 – 2019
- 2019
- [c14]Neil Veira, Brian Keng, Kanchana Padmanabhan, Andreas G. Veneris:
Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. IJCAI 2019: 5218-5225 - [i2]Thang Doan, Neil Veira, Brian Keng:
Generating Realistic Sequences of Customer-level Transactions for Retail Datasets. CoRR abs/1901.05577 (2019) - 2018
- [c13]Tianle Chen, Brian Keng, Javier Moreno:
Multivariate Arrival Times with Recurrent Neural Networks for Personalized Demand Forecasting. ICDM Workshops 2018: 810-819 - [c12]Thang Doan, Neil Veira, Brian Keng:
Generating Realistic Sequences of Customer-Level Transactions for Retail Datasets. ICDM Workshops 2018: 820-827 - [i1]Tianle Chen, Brian Keng, Javier Moreno:
Multivariate Arrival Times with Recurrent Neural Networks for Personalized Demand Forecasting. CoRR abs/1812.11444 (2018) - 2014
- [c11]Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le:
Automated debugging of missing assumptions. ASP-DAC 2014: 732-737 - 2013
- [j2]Brian Keng, Andreas G. Veneris:
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1609-1622 (2013) - 2012
- [c10]Brian Keng, Andreas G. Veneris:
Path directed abstraction and refinement in SAT-based design debugging. DAC 2012: 947-954 - [c9]Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris:
Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE 2012: 629-634 - [c8]Brian Keng, Andreas G. Veneris:
Automated debugging of missing input constraints in a formal verification environment. FMCAD 2012: 101-105 - 2011
- [c7]Andreas G. Veneris, Brian Keng, Sean Safarpour:
From RTL to silicon: The case for automated debug. ASP-DAC 2011: 306-310 - [c6]Brian Keng, Andreas G. Veneris:
Managing complexity in design debugging with sequential abstraction and refinement. ASP-DAC 2011: 479-484 - [c5]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Automated debugging of SystemVerilog assertions. DATE 2011: 323-328 - 2010
- [j1]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Bounded Model Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1790-1803 (2010) - [c4]Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682 - [c3]Brian Keng, Andreas G. Veneris, Sean Safarpour:
An Automated Framework for Correction and Debug of PSL Assertions. MTV 2010: 9-12
2000 – 2009
- 2009
- [c2]Brian Keng, Andreas G. Veneris:
Scaling VLSI design debugging with interpolation. FMCAD 2009: 144-151 - 2008
- [c1]Brian Keng, Hratch Mangassarian, Andreas G. Veneris:
A succinct memory model for automated design debugging. ICCAD 2008: 137-142
Coauthor Index
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