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2010 – 2019
- 2010
[j4]Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu
, Chih-Tsun Huang:
Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 541-552 (2010)
2000 – 2009
- 2005
- [c6]Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu:
A configurable AES processor for enhanced security. ASP-DAC 2005: 361-366 - [c5]Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
Design and test of a scalable security processor. ASP-DAC 2005: 372-375 - 2004
- [j3]Chih-Pin Su, Cheng-Wen Wu:
A Graph-Based Approach to Power-Constrained SOC Test Scheduling. J. Electron. Test. 20(1): 45-60 (2004) - [c4]Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms. ASP-DAC 2004: 456-458 - 2003
- [j2]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A high-throughput low-cost AES processor. IEEE Commun. Mag. 41(12): 86-91 (2003) - [c3]Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
Design of a scalable RSA and ECC crypto-processor. ASP-DAC 2003: 495-498 - [c2]Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A highly efficient AES cipher chip. ASP-DAC 2003: 561-562 - 2002
- [j1]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5): 69-81 (2002) - [c1]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs. DATE 2002: 486-490
Coauthor Index
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