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2020 – today
- 2024
[c8]Luca Zulberti, Andrea Monorchio, Matteo Monopoli, Gabriela Mystkowska, Pietro Nannipieri, Luca Fanucci:
SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems. DSD 2024: 306-313- [c7]Gabriela Mystkowska, Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci:
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine. DSD 2024: 314-318 - 2023
- [c6]Stefano Di Matteo
, Luca Zulberti, Federico Cosimo Lapenna, Pietro Nannipieri, Luca Crocetti, Luca Fanucci, Sergio Saponara:
A PUF-Based Secure Boot for RISC-V Architectures. ApplePies 2023: 87-94 - [c5]Pietro Nannipieri, Stefano Di Matteo, Luca Crocetti, Luca Zulberti, Luca Fanucci, Sergio Saponara:
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative. ApplePies 2023: 378-385 - [c4]Giovanni Todaro, Matteo Monopoli, Gionata Benelli, Luca Zulberti, Tommaso Pacini:
Enhanced Soft GPU Architecture for FPGAs. PRIME 2023: 177-180 - [c3]Matteo Monopoli, Luca Zulberti, Giovanni Todaro, Pietro Nannipieri, Luca Fanucci:
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip. PRIME 2023: 181-184 - 2022
- [j2]Pietro Nannipieri, Stefano Di Matteo, Luca Baldanzi, Luca Crocetti, Luca Zulberti, Sergio Saponara, Luca Fanucci:
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative. IEEE Trans. Very Large Scale Integr. Syst. 30(2): 177-186 (2022) - [c2]Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci:
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators. PRIME 2022: 373-376 - 2021
- [j1]Pietro Nannipieri, Stefano Di Matteo, Luca Zulberti, Francesco Albicocchi, Sergio Saponara, Luca Fanucci:
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. IEEE Access 9: 150798-150808 (2021) - [c1]Luca Zulberti, Pietro Nannipieri, Luca Fanucci:
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. DTIS 2021: 1-6
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last updated on 2024-11-20 20:58 CET by the dblp team
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