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ORCIDSoyoun Jeong
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2020 – today
- 2022
[j2]Soyoun Jeong
, Jaerok Kim, Minhyeok Jeong, Yoonmyung Lee:
Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2845-2856 (2022)- [c3]Seonho Kim, Changyoun Im, Jongmin Lee, Soyoun Jeong, Jaerok Kim, Yoonmyung Lee:
Logic-embedded Physically Unclonable Functions for Synthesizable and Periphery-free Implementation for Low Area and Design Cost IoT Security. ESSCIRC 2022: 521-524 - 2021
- [j1]Eunyoung Lee, Taeyoung Han, Donguk Seo, Gicheol Shin, Jaerok Kim, Seonho Kim, Soyoun Jeong, Johnny Rhe, Jaehyun Park, Jong Hwan Ko, Yoonmyung Lee:
A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators. IEEE Trans. Circuits Syst. I Regul. Pap. 68(8): 3305-3316 (2021) - [c2]Gicheol Shin, Donguk Seo, Jaerok Kim, Johnny Rhe, Eunyoung Lee, Seonho Kim, Soyoun Jeong, Jong Hwan Ko, Yoonmyung Lee:
A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. ESSCIRC 2021: 123-126 - [c1]Gicheol Shin, Donguk Seo, Jaerok Kim, Johnny Rhe, Eunyoung Lee, Seonho Kim, Soyoun Jeong, Jong Hwan Ko, Yoonmyung Lee:
A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions. ESSDERC 2021: 123-126
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