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ORCIDSeongjae Cho
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2020 – today
- 2024
[c3]Soomin Kim, Seongjae Cho:
Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET. ICEIC 2024: 1-2- 2023
- [j25]Arati Kumari Shah
, Eou-Sik Cho, Jisun Park, Hyungsoon Shin, Seongjae Cho:
A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement. IEEE Access 11: 53932-53938 (2023) - [j24]Kannan Udaya Mohanan, Seongjae Cho, Byung-Gook Park:
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application. Appl. Intell. 53(6): 6288-6306 (2023) - [j23]Arati Kumari Shah, Kannan Udaya Mohanan, Jisun Park, Hyungsoon Shin, Eou-Sik Cho, Seongjae Cho:
An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network. IET Circuits Devices Syst. 2023: 1-10 (2023) - 2021
- [j22]Dongyeon Kang, Jun Tae Jang, Shinyoung Park, Md. Hasan Raza Ansari, Jong-Ho Bae, Sung-Jin Choi, Dong Myong Kim, Changwook Kim, Seongjae Cho, Dae Hwan Kim:
Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System. IEEE Access 9: 59345-59352 (2021) - 2020
- [j21]Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim:
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. IEEE Access 8: 130678-130686 (2020) - [j20]Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Kyungho Hong, Chae Soo Kim, Sungjun Kim, Seongjae Cho, Byung-Gook Park:
Insertion of Ag Layer in TiN/SiNx/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation. IEEE Access 8: 228720-228730 (2020)
2010 – 2019
- 2018
- [c2]Jae Yoon Lee, Youngmin Kim, Ikhyeon Kworn, Il Hwan Cho, Jae Yeon Lee, Soo Gil Kim, Seongjae Cho:
Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory. DRC 2018: 1-2 - 2016
- [j19]Sungjun Kim, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park:
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell. IEICE Trans. Electron. 99-C(5): 547-550 (2016) - 2015
- [j18]Sungjun Kim, Sunghun Jung, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park:
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals. IEICE Trans. Electron. 98-C(5): 429-433 (2015) - [c1]Mina Yun, Seongjae Cho, Sae-Kyoung Kang, Sunghun Jung, Byung-Gook Park:
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect. ISCE 2015: 1-2 - 2014
- [j17]Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park:
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access. IEICE Electron. Express 11(4): 20131041 (2014) - [j16]Sung Yun Woo, Young Jun Yoon, Jae Hwa Seo, Gwan Min Yoo, Seongjae Cho, In Man Kang:
InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate. IEICE Trans. Electron. 97-C(7): 677-682 (2014) - 2012
- [j15]Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park, James S. Harris Jr.:
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance. IEICE Electron. Express 9(9): 828-833 (2012) - 2011
- [j14]Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park:
A New 1T DRAM Cell: Cone Type 1T DRAM Cell. IEICE Trans. Electron. 94-C(5): 681-685 (2011) - 2010
- [j13]Seongjae Cho, In Man Kang, Kyung Rok Kim:
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs. IEICE Electron. Express 7(19): 1499-1503 (2010) - [j12]Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park:
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer. IEICE Trans. Electron. 93-C(5): 540-545 (2010) - [j11]Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park:
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. IEICE Trans. Electron. 93-C(5): 596-601 (2010)
2000 – 2009
- 2009
- [j10]Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park:
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). IEICE Trans. Electron. 92-C(5): 620-626 (2009) - [j9]Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park:
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. IEICE Trans. Electron. 92-C(5): 647-652 (2009) - [j8]Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park:
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. IEICE Trans. Electron. 92-C(5): 653-658 (2009) - [j7]Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park:
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. IEICE Trans. Electron. 92-C(5): 659-663 (2009) - [j6]Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho:
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. Microelectron. J. 40(4-5): 769-772 (2009) - 2008
- [j5]Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park:
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Trans. Electron. 91-C(5): 731-735 (2008) - [j4]Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park:
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Trans. Electron. 91-C(5): 742-746 (2008) - 2007
- [j3]Hochul Lee, Youngchang Yoon, Seongjae Cho, Hyungcheol Shin:
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. IEICE Trans. Electron. 90-C(5): 968-972 (2007) - [j2]Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park:
Design and Simulation of Asymmetric MOSFETs. IEICE Trans. Electron. 90-C(5): 978-982 (2007) - [j1]Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park:
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Trans. Electron. 90-C(5): 988-993 (2007)
Coauthor Index
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