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ORCIDYibo Wang 0009
Person information
- affiliation: Tsinghua University, Department of Computer Science and Technology, Beijing, China
Other persons with the same name
- Yibo Wang (aka: Yi-Bo Wang) — disambiguation page
- Yibo Wang 0001
![[0000-0001-8872-1811]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0001-8872-1811")
— University of Illinois Chicago (UIC), Department of Computer Science, Chicago, IL, USA - Yibo Wang 0002 — Chinese Academy of Sciences, Institute of Geology and Geophysics, Beijing, China (and 1 more)
- Yibo Wang 0003 — Pohang University of Science and Technology (POSTECH), Gyeongbuk, Republic of Korea (and 1 more)
- Yibo Wang 0004 — Nanjing University, School of Electronic Sciene and Engineering, Nanjing, China
- Yibo Wang 0005 — Nanjing University, National Key Laboratory for Novel Software Technology, Nanjing, China (and 1 more)
- Yibo Wang 0006 — Syracuse University, FullStack Security Lab, Syracuse, NY, USA
- Yibo Wang 0007 — Renmin University of China, School of Information, Beijing, China
- Yibo Wang 0008 — Northeastern University, Shenyang, China
- Yibo Wang 0010 — Southeast University, School of Mathematics, Nanjing, China
- Yibo Wang 0011 — Chinese Academy of Sciences, Changchun Institute of Applied Chemistry, Laboratory of Chemical Biology, Changchun, China
- Yibo Wang 0012 — Dalian University of Technology, School of Software, Dalian, China
- Yibo Wang 0013 — University of Virginia, Department of Chemistry, Charlottesville, VA, USA
- Yibo Wang 0014 — Chinese Academy of Sciences, Aerospace Information Research Institute, Beijing, China (and 1 more)
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2000 – 2009
- 2008
[c6]Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775- [c5]Yibo Wang, Yici Cai, Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226 - 2007
- [j1]Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 1028-1037 (2007) - 2006
- [c4]Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006 - [c3]Yibo Wang, Yici Cai, Xianlong Hong:
Performance and power aware buffered tree construction. ISCAS 2006 - 2005
- [c2]Yici Cai, Yibo Wang, Xianlong Hong:
A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96 - [c1]Yibo Wang, Yici Cai, Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96
Coauthor Index
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